LPC2102FHN48,551 NXP Semiconductors, LPC2102FHN48,551 Datasheet - Page 18
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LPC2102FHN48,551
Manufacturer Part Number
LPC2102FHN48,551
Description
IC ARM7 MCU FLASH 16K 48-HVQFN
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2102FHN48551.pdf
(37 pages)
Specifications of LPC2102FHN48,551
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Core Processor
ARM7
Core Size
16/32-Bit
Speed
70MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
4 KB
Interface Type
I2C/JTAG/SPI/SSP/UART
Maximum Clock Frequency
70 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2MCB2103 - BOARD EVAL NXP LPC2101/2101/2103622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4689
935286982551
LPC2102FHN48-S
935286982551
LPC2102FHN48-S
NXP Semiconductors
LPC2101_02_03_4
Product data sheet
6.17.3 Reset and wake-up timer
Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST
pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by
any source starts the wake-up timer (see wake-up timer description below), causing the
internal chip reset to remain asserted until the external reset is de-asserted, the oscillator
is running, a fixed number of clocks have passed, and the on-chip flash controller has
completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined reset values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down and Deep power-down mode, any wake-up of the processor from
the Power-down modes makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
Rev. 04 — 2 June 2009
DD
ramp (in the case of power on), the type of crystal
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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