LPC3130FET180,551 NXP Semiconductors, LPC3130FET180,551 Datasheet - Page 7

• Manufacturer Part Number: LPC3130FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3130FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: LPC3000
• Device Core: ARM926EJ-S
• Device Core Size: 16/32Bit
• Frequency (max): 180MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 96KB
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/2.8/3.3/5V
• Operating Supply Voltage (max): 1.3/3.6V
• Operating Supply Voltage (min): 1/1.1/1.65/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 180
• Package Type: TFBGA
• Package: 180TFBGA
• Family Name: LPC3000
• Maximum Speed: 180 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4696; 935288013551; LPC3130FET180-S

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3130_3131
Preliminary data sheet
Pin name
USB_DM
USB_VDDA12_PLL
USB_VDDA33_DRV
USB_VDDA33
USB_VSSA_TERM
USB_GNDA
USB_VSSA_REF
JTAG
JTAGSEL
TDI
TRST_N
TCK
TMS
SCAN_TDO
ARM_TDO
BUF_TRST_N
BUF_TCK
BUF_TMS
UART
mUART_CTS_N
mUART_RTS_N
UART_RXD
UART_TXD
I
I2C_SDA0
I2C_SCL0
I2C_SDA1
I2C_SCL1
2
C master/slave interface
[4]
[4]
Pin description
[4]
[4]
[4][5]
[4][5]
BGA
ball
N2
L1
M2
P1
L3
N1
K4
N11
K9
P13
M14
P10
F10
E11
F11
D13
D14
N13
P14
P12
N12
C10
D10
E12
E13
Digital
I/O
level
[1]
SUP3
SUP1
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
All information provided in this document is subject to legal disclaimers.
Application
function
AIO
Supply
Supply
Supply
Ground
Ground
Ground
DI
DI
DI
DI
DI
DO
DO
DO
DO
DO
DI / GPIO
DO / GPIO
DI / GPIO
DO / GPIO
DIO
DIO
DIO
DIO
Rev. 1.04 — 27 May 2010
Table 10
Pin
state
after
reset
-
-
-
-
-
-
-
I:PD
I:PU
I:PD
I:PD
I:PU
O/Z
O
O
O
O
I
O
I
O
I
I
O
O
for pin function selection of multiplexed pins.
Low-cost, low-power ARM926EJ-S microcontrollers
[2]
Cell type
[3]
AIO1
PS3
PS3
PS3
CG1
CG1
CG1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
IICD
IICC
DIO1
DIO1
Description
USB D− connection with integrated 45 Ω
termination resistor
USB PLL supply
USB Analog supply for driver
USB Analog supply for PHY
USB Analog ground for clean reference for
on chip termination resistors
USB Analog ground
USB Analog ground for clean reference
JTAG selection. Controls output function of
SCAN_TDO and ARM_TDO signals. Must be
LOW during power-on reset.
JTAG Data Input
JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
JTAG Clock Input
JTAG Mode Select Input
JTAG TDO signal from scan TAP controller.
Pin state is controlled by JTAGSEL.
JTAG TDO signal from ARM926 TAP
controller.
Buffered TRST_N out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
Buffered TCK out signal. Used for connecting
an on board TAP controller (FPGA, DSP,
etc.).
Buffered TMS out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
UART Clear To Send (active LOW)
UART Ready To Send (active LOW)
UART Serial Input
UART Serial Output
I
I
I
I
2
2
2
2
C Data Line
C Clock line
C Data Line
C Clock line
LPC3130/3131
© NXP B.V. 2010. All rights reserved.
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