LPC2220FBD144,551 NXP Semiconductors, LPC2220FBD144,551 Datasheet - Page 22

• Manufacturer Part Number: LPC2220FBD144,551
• Description: IC ARM7 MCU RAM 64K 144-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2220FBD144,551

• Program Memory Type: ROMless
• Package / Case: 144-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC22
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C/SPI/SSP/UART
• Maximum Clock Frequency: 75 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM10091
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 144LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 75 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1896; 935278829551; LPC2220FBD144-S

NXP Semiconductors
Table 9.
LPC2210_2220_6
Product data sheet
PINSEL2 bits
1:0
2
3
5:4
6
7
8
10:9
11
12
13
15:14
17:16
19:18
20
21
22
Pin function select register 2 (PINSEL2 - 0xE002 C014)
6.8 Pin function select register 2 (PINSEL2 - 0xE002 C014)
Description
reserved
When 0, pins P1[36:26] are used as GPIO pins. When 1, P1[31:26] are used as a
Debug port.
When 0, pins P1[25:16] are used as GPIO pins. When 1, P1[25:16] are used as a
Trace port.
Controls the use of the data bus and strobe pins:
Pins P2[7:0]
Pin P1.0
Pin P1.1
Pin P3.31
Pins P2[15:8]
Pin P3.30
Pins P2[27:16]
Pins P2[29:28]
Pins P2[31:30]
Pins P3[29:28]
If bits 5:4 are not 10, controls the use of pin P3.29: 0 enables P3.29, 1 enables
AIN6.
If bits 5:4 are not 10, controls the use of pin P3.28: 0 enables P3.28, 1 enables
AIN7.
Controls the use of pin P3.27: 0 enables P3.27, 1 enables WE.
reserved
Controls the use of pin P3.26: 0 enables P3.26, 1 enables CS1.
reserved
If bits 27:25 are not 111, controls the use of pin P3.23/A23/XCLK: 0 enables P3.23,
1 enables XCLK.
Controls the use of pin P3.25: 00 enables P3.25, 01 enables CS2, 10 and 11 are
reserved values.
Controls the use of pin P3.24: 00 enables P3.24, 01 enables CS3, 10 and 11 are
reserved values.
reserved
If bits 5:4 are not 10, controls the use of pin P2[29:28]: 0 enables P2[29:28], 1 is
reserved
If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables
AIN4.
If bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables
AIN5.
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table
function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in
9. The direction control bit in the IODIR register is effective only when the GPIO
00 or 11 = P2[15:8]
00 or 11 = P3.30
0x or 11 = P2[27:16]
0x or 11 = P2[29:28]
0x or 11 = P2[31:30] or AIN5 to
0x or 11 = P3[29:28] or AIN7 to
11 = P2[7:0]
11 = P1.0
11 = P1.1
11 = P3.31
Rev. 06 — 11 December 2008
AIN4
AIN6
Table 9
are reserved, and should not be used.
01 or 10 = D15 to D8
01 or 10 = BLS1
0x or 10 = D7 to D0
0x or 10 = CS0
0x or 10 = OE
0x or 10 = BLS0
10 = D27 to D16
10 = D29, D28
10 = D31, D30
10 = BLS2, BLS3
16/32-bit ARM microcontrollers
LPC2210/2220
Reset value
-
P1.26/RTCK
P1.20/
TRACESYNC
BOOT1:0
1
1
0
-
0
-
0
00
00
-
0
1
1
© NXP B.V. 2008. All rights reserved.
22 of 50