LPC2109FBD64/01,15 NXP Semiconductors, LPC2109FBD64/01,15 Datasheet - Page 23
![IC ARM7 MCU FLASH 64K 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
LPC2109FBD64/01,15
Manufacturer Part Number
LPC2109FBD64/01,15
Description
IC ARM7 MCU FLASH 64K 64-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2109FBD640115.pdf
(44 pages)
Specifications of LPC2109FBD64/01,15
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
46
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC21
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
8 KB
Interface Type
CAN/I2C/JTAG/SPI/SSP/UART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
46
Number Of Timers
2
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
64LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
60 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4310 - EVAL BOARD LPC2158 W/LCD568-4297 - BOARD EVAL LPC21XX MCB2100622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4311
935284891151
LPC2109FBD64/01-S
LPC2109FBD64/01-S
935284891151
LPC2109FBD64/01-S
LPC2109FBD64/01-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2109FBD64/01,15
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Product data sheet
LPC2109_2119_2129_6
6.18.8 APB
6.19.1 EmbeddedICE
6.19.2 Embedded trace macrocell
6.19 Emulation and debugging
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at
processor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
The LPC2109/2119/2129 support emulation and debugging via a JTAG serial port. A trace
port allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
interface to operate.
Since the LPC2109/2119/2129 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The ETM provides real-time trace capability for deeply embedded processor
cores. It outputs information about processor execution to the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
1
2
to
1
4
of the processor clock rate. Because the APB must work properly at
Rev. 06 — 10 December 2007
1
6
of the CPU clock (CCLK) for the JTAG
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
1
4
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