ADUC7024BSTZ62 Analog Devices Inc, ADUC7024BSTZ62 Datasheet - Page 75

• Manufacturer Part Number: ADUC7024BSTZ62
• Description: IC MCU FLASH 62K ANLG I/O 64LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BSTZ62

• Core Size: 16/32-Bit
• Program Memory Size: 62KB (62K x 8)
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 30
• Ram Memory Size: 8KB
• Cpu Speed: 44MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 44 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 23 interrupt sources on the ADuC7019/20/21/22/
24/25/26/27/28 that are controlled by the interrupt controller.
Most interrupts are generated from the on-chip peripherals,
such as ADC and UART. Four additional interrupt sources are
generated from external interrupt request pins, IRQ0, IRQ1,
IRQ2, and IRQ3. The ARM7TDMI CPU core only recognizes
interrupts as one of two types, a normal interrupt request IRQ
or a fast interrupt request FIQ. All the interrupts can be masked
separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ registers (except for Bit 23) represent
the same interrupt source as described in Table 73.
Table 73. IRQ/FIQ MMRs Bit Description
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Description
SWI.
Timer0.
Timer1.
Wake-Up Timer (Timer2).
Watchdog Timer (Timer3).
Flash Control.
ADC Channel.
PLL Lock.
I2C0 Slave.
I2C0 Master.
I2C1 Master.
SPI Slave.
SPI Master.
UART.
External IRQ0.
Comparator.
External IRQ1.
External IRQ2.
External IRQ3.
All Interrupts OR’ed (FIQ only).
PSM.
PLA IRQ0.
PLA IRQ1.
PWM Trip (IRQ only)/PWM Sync (FIQ only).
Rev. B | Page 75 of 92
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are: IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
IRQSTA Register
Name
IRQSTA
IRQSTA (read-only register) provides the current-enabled IRQ
source status. When set to 1, that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ e d to create the IRQ signal
to the ARM7TDMI core.
IRQSIG Register
Name
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the IRQSIG
is set; otherwise, it is cleared. The IRQSIG bits are cleared when
the interrupt in the particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR. IRQSIG is read-only.
IRQEN Register
Name
IRQEN
IRQEN provides the value of the current enable mask. When
each bit is set to 1, the source request is enabled to create an
IRQ exception. When each bit is set to 0, the source request is
disabled or masked, which does not create an IRQ exception.
Note that to clear an already enabled interrupt source, users
must set the appropriate bit in the IRQCLR register. Clearing an
interrupt’s IRQEN bit does not disable this interrupt.
IRQCLR Register
Name
IRQCLR
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
ADuC7019/20/21/22/24/25/26/27/28
Address
0xFFFF0000
Address
0xFFFF0004
Address
0xFFFF0008
Address
0xFFFF000C
Default Value
0x00000000
Default Value
0x00XXX000
Default Value
0x00000000
Default Value
0x00000000
Access
R
Access
R
Access
R/W
Access
W