LPC2377FBD144,551 NXP Semiconductors, LPC2377FBD144,551 Datasheet - Page 50

• Manufacturer Part Number: LPC2377FBD144,551
• Description: IC ARM7 MCU FLASH 512K 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2377FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 58K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: LPC23
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 58 KB
• Interface Type: CAN, I2S, ISP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 144LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 568-4310 - EVAL BOARD LPC2158 W/LCDMCB2370UME - BOARD EVAL MCB2370 + ULINK-MEMCB2370U - BOARD EVAL MCB2370 + ULINK2MCB2370 - BOARD EVAL NXP LPC2368/2378568-3999 - BOARD EVAL FOR LPC23 ARM MCU622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4411; 935286019551; LPC2377FBD144-S

Table 12.
C
[1]
[2]
[3]
[4]
[5]
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
CSLBLSL
BLSDV
CSLDV
BLSLBLSH
BLSHANV
BLSHDNV
L
= 30 pF, T
V
V
T
Latest of address valid, CS LOW, OE LOW to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
OH
IH
cy(CCLK)
= 2.5 V, V
= 2.5 V, V
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
CS LOW to BLS LOW time
BLS LOW to data valid time
CS LOW to data valid time
BLS LOW to BLS HIGH
time
BLS HIGH to address
invalid time
BLS HIGH to data invalid
time
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Dynamic characteristics: Static external memory interface
=
amb
1
⁄
CCLK
IL
11.5 Static external memory interface
=
OL
= 0.5 V.
−
.
= 0.2 V.
40
°
C to 85
[1][2]
[1]
°
C, V
[1]
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3][4]
[5]
[3]
[3]
[3]
= 3.0 V to 3.6 V, AHB clock = 1 MHz
Min
−0.29
−0.29
−0.78 + T
(WAITRD − WAITOEN + 1) ×
T
0
−0.49
−0.20
−0.59 + (WAITRD −
WAITOEN + 1) × T
−0.88 + T
WAITWEN)
0.68
0
−0.78 + T
(WAITWR − WAITWEN + 1)
0 + T
0.78
cy(CCLK)
cy(CCLK)
− 8.11
cy(CCLK)
cy(CCLK)
cy(CCLK)
× WAITOEN 0 + T
× (1 +
×
cy(CCLK)
Typ
0.20
0.20
(WAITRD − WAITOEN + 1) ×
T
-
0
0.20
0 + (WAITRD − WAITOEN +
1) × T
0.10 + T
WAITWEN)
2.54
2.64
0 + T
WAITWEN + 1)
0.20 + T
2.54
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 9.57
× WAITOEN
× (WAITWR −
× (1 +
0.49 + T
5.86
Max
2.54
2.54
(WAITRD − WAITOEN + 1) ×
T
-
0.20
2.44
0.10 + (WAITRD −
WAITOEN + 1) × T
0.20 + T
WAITWEN)
4.79
0.10 + T
(WAITWR − WAITWEN + 1)
2.74 + T
5.96
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 12.70
× WAITOEN
× (1 +
×
cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns