Z8F042AHH020SC Zilog, Z8F042AHH020SC Datasheet - Page 187
![IC ENCORE XP MCU FLASH 4K 20SSOP](/photos/9/30/93032/269-20-ssop_sml.jpg)
Z8F042AHH020SC
Manufacturer Part Number
Z8F042AHH020SC
Description
IC ENCORE XP MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F042AHH020SC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3369
- Current page: 187 of 282
- Download datasheet (4Mb)
PS022825-0908
START
Note:
OCD Data Format
OCD Auto-Baud Detector/Generator
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
The OCD interface uses the asynchronous data format defined for RS-232. Each character
transmitted and received by the OCD consists of 1 Start bit, 8 data bits (least-significant
bit first), and 1 Stop bit as displayed in
When responding to a request for data, the OCD may commence transmitting immediately
after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the
host must not actively drive the DBG pin High for more than 0.5 bit times. It is recom-
mended that, if possible, the host drives the DBG pin using an open drain output to avoid
this issue.
To run over a range of baud rates (data bits per second) with various system clock
frequencies, the On-Chip Debugger contains an Auto-Baud Detector/Generator. After a
reset, the OCD is idle until it receives data. The OCD requires that the first character sent
from the host is the character
Start bit plus 7 data bits), framed between High bits. The Auto-Baud Detector measures
this period and sets the OCD Baud Rate Generator accordingly.
D0
•
•
•
•
•
•
•
DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled High.
At this point, the PA0/DBG pin may be used to autobaud and cause the device to enter
DEBUG mode. See
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
Voltage Brownout reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP mode initiates a System Reset
If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/
D1
Figure 26. OCD Data Format
D2
OCD Unlock Sequence (8-Pin Devices Only)
80H
D3
. The character
Figure
D4
26.
80H
D5
has eight continuous bits Low (one
Z8 Encore! XP
D6
Product Specification
D7
®
On-Chip Debugger
on page 178.
F082A Series
STOP
176
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