ST7FLITE25F2B6 STMicroelectronics, ST7FLITE25F2B6 Datasheet - Page 41

• Manufacturer Part Number: ST7FLITE25F2B6
• Description: IC MCU 8BIT 8K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE25F2B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13 bit
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-4858

POWER SAVING MODES (Cont’d)
9.4.1 Halt Mode Recommendations
– Make sure that an external event is available to
– When using an external interrupt to wake up the
– For the same reason, reinitialize the level sensi-
– The opcode for the HALT instruction is 0x8E. To
– As the HALT instruction clears the interrupt mask
wake up the microcontroller from Halt mode.
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
tiveness of each external interrupt as a precau-
tionary measure.
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro-
gram memory with the value 0x8E.
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
9.5 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction. The decision to enter either in ACTIVE-
HALT or HALT mode is given by the LTCSR/ATC-
SR register status as shown in the following table:
The MCU can exit ACTIVE-HALT mode on recep-
tion of a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 35) or a RESET.
– When exiting ACTIVE-HALT mode by means of
– When exiting ACTIVE-HALT mode by means of
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately (see Note 3).
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Note: As soon as ACTIVE-HALT is enabled, exe-
cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
TB1IE bit
LTCSR1
a RESET, a 256 or 4096 CPU cycle delay oc-
curs. After the start up delay, the CPU resumes
operation by fetching the reset vector which
woke it up (see
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see
0
0
1
x
ATCSR
OVFIE
Figure
bit
x
0
x
1
Figure
ATCSR
CK1 bit
27).
0
x
x
x
27).
CK0 bit
ATCSR
0
1
x
x
ACTIVE-HALT
mode disabled
ACTIVE-HALT
mode enabled
ST7LITE2
Meaning
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