EZ80F92AZ020SG Zilog, EZ80F92AZ020SG Datasheet - Page 141
![IC ACCLAIM MCU 128KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F92AZ020SG
Manufacturer Part Number
EZ80F92AZ020SG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3872
EZ80F92AZ020SG
EZ80F92AZ020SG
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PS015313-0508
SPI Flags
SPI Baud Rate Generator
Mode Fault
The Mode Fault flag (MODF) indicates that there may be a multimaster conflict for sys-
tem control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault flag is cleared.
Write Collision
The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made
to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing
the WCOL bit is performed by reading SPI_SR with the WCOL bit set.
The SPI’s Baud Rate Generator creates a lower frequency clock from the high-frequency
system clock. The Baud Rate Generator output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit registers, and
associated decoding logic. The Baud Rate Generator’s initial value is defined by the two
BRG Divisor Latch registers, {SPI_BRG_H, SPI_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value
clock rising edge, the BRG reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and
outputs a pulse to indicate the end-of-count. Calculate the SPI Data Rate with the follow-
ing equation:
SPI Data Rate (bps)
mode.
interrupt is generated.
=
System Clock Frequency
2 X SPI Baud Rate Generator Divisor
0001h
Product Specification
Serial Peripheral Interface
. On the next system
eZ80F92/eZ80F93
134
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