EZ80F92AZ020SG Zilog, EZ80F92AZ020SG Datasheet - Page 47
![IC ACCLAIM MCU 128KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F92AZ020SG
Manufacturer Part Number
EZ80F92AZ020SG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3872
EZ80F92AZ020SG
EZ80F92AZ020SG
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Part Number
Manufacturer
Quantity
Price
Company:
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EZ80F92AZ020SG
Manufacturer:
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Quantity:
20
Company:
Part Number:
EZ80F92AZ020SG
Manufacturer:
MAX
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Table 6. GPIO Mode Selection (Continued)
PS015313-0508
GPIO
Mode
2
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GPIO Mode 1—
ten to the Port x Data register (Px_DR) is presented on the pin.
GPIO Mode 2—
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a Read from the Port x Data register returns the pin’s value. GPIO Mode
2 is the default operating mode following a RESET.
GPIO Mode 3—
ture an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4—
ture an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-
SOURCE mode, an external pull-down resistor must connect the pin to the supply ground.
Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x
Data register results in a high-impedance output.
Px_ALT1
Bits7:0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Px_DDR
The port pin is configured as a standard digital output pin. The value writ-
The port pin is configured as a standard digital input pin. The output is
The port pin is configured as open-drain I/O. The GPIO pins do not fea-
The port pin is configured as open-source I/O. The GPIO pins do not fea-
Bits7:0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Px_DR
Bits7:0 Port Mode
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input from pin
Input from pin
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
Interrupt—dual edge triggered
Port B, C, or D—alternate function controls port I/O
Port B, C, or D—alternate function controls port I/O
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge triggered
Interrupt—rising edge triggered
General-Purpose Input/Output
Product Specification
eZ80F92/eZ80F93
Output
High impedance
High impedance
0
High impedance
High impedance
1
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
40
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