Z16F2810FI20SG Zilog, Z16F2810FI20SG Datasheet - Page 322
Z16F2810FI20SG
Manufacturer Part Number
Z16F2810FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2810FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4567
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F2810FI20SG
Manufacturer:
Zilog
Quantity:
211
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PS022008-0810
Debug Lock
Error Reset
Internal
System Reset
Debug Reset
Debug Pin
Reset Pin
The interface has a locking mechanism to prevent user code from disabling the OCD and
using the DBG pin as a UART or GPIO pin. The
prevents you from disabling the OCD and modifying any register that would inhibit
communication with the OCD. The default state of the
the
In order to use the DBG pin as a UART or GPIO pin, you must program the
option bit to zero so the
register is unlocked, software then clears the
UART or GPIO pin.
If the
locked before code has the chance to disable the OCD. This is done by initializing the
Debugger during reset and writing the
The serial interface has an Auto-Reset mechanism that resets the serial interface when a
Transmit Collision or Receive Framing Error is detected. When a Transmit Collision or
Receive Framing Error is detected when
currently in progress, transmits a Serial Break condition for 4096 system clocks, and sets
the
the error.
A clock change invalidates the baud reload value. Communication cannot continue until a
new autobaud reload value is set. As a result, the device automatically sends a serial break
to reset the communication link whenever a clock change occurs.
DBGUART
ABSRCH
DBGUART
bit in the DBGCTL register. This break is sent to ensure the host also detects
option bit.
Reset Timeout
option bit is cleared and the
Figure 68. Initialization during Reset
OCDLOCK
P R E L I M I N A R Y
control bit is cleared after reset. After the control
OCDLOCK
OCDEN
80H
Reset Pin Remains Asserted
OCDLOCK
OCDEN
is set, the OCD aborts any command
control bit to 1.
DBGLOCK
00H
control bit to use the DBG pin as a
control bit is not set, the
DBGLOCK
IDH
bit in the DBGCTL register
Product Specification
IDL
bit is set accordingly to
ZNEO
On-Chip Debugger
Z16F Series
DBGUART
OCD
is still
306
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