C8051F332-GM Silicon Laboratories Inc, C8051F332-GM Datasheet - Page 55

IC 8051 MCU 4KB FLASH 20QFN

C8051F332-GM

Manufacturer Part Number
C8051F332-GM
Description
IC 8051 MCU 4KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheets

Specifications of C8051F332-GM

Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
20QFN
Device Core
8051
Family Name
C8051F33x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1266

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F332-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
Part Number:
C8051F332-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
C8051F330/1/2/3/4/5
6.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen-
dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event.
This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling
rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the
IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both
IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0,
Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to
the IDAC input latches, allowing the IDAC output to change to the new value.
6.1.3. Update Output Based on CNVSTR Edge
The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the
external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to
both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The
particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or
both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the
IDAC input latches, allowing the IDAC output to change to the new value.
6.2.
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC
output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are
mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 6.2.
The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default,
the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide
full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 6.1.
58
Input Data Word
D9
IDAC Output Mapping
(D9–D0)
0x3FF
0x000
0x001
0x200
D8
D7
D6
IDA0H
IDA0OMD[1:0] = ‘1x’
1023/1024 x 2 mA
512/1024 x 2 mA
Output Current
1/1024 x 2 mA
Figure 6.2. IDA0 Data Word Mapping
D5
0 mA
D4
D3
D2
Rev. 1.7
IDA0OMD[1:0] = ‘01’
1023/1024 x 1 mA
512/1024 x 1 mA
Output Current
D1
1/1024 x 1 mA
0 mA
D0
IDA0L
IDA0OMD[1:0] = ‘00’
1023/1024 x 0.5 mA
512/1024 x 0.5 mA
1/1024 x 0.5 mA
Output Current
0 mA

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