C8051F996-GM Silicon Laboratories Inc, C8051F996-GM Datasheet - Page 170
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C8051F996-GM
Manufacturer Part Number
C8051F996-GM
Description
IC MCU 8BIT 8KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F996-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1943-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F996-GM
Manufacturer:
SILICON
Quantity:
570
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C8051F99x-C8051F98x
16. Cyclic Redundancy Check Unit (CRC0)
C8051F99x-C8051F98x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC
using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts
the 16-bit result to an internal register. The internal result register may be accessed indirectly using the
CRC0PNT bits and CRC0DAT register, as shown in Figure 16.1. CRC0 also has a bit reverse register for
quick data manipulation.
16.1. CRC Algorithm
The C8051F99x-C8051F98x CRC unit generates a CRC result equivalent to the following algorithm:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the
2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected
2b. If the MSB of the CRC result is not set, shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-
ple.
170
CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
polynomial.
CRC0FLIP
CRC0FLIP
CRC0PNT0
CRC0SEL
CRC0INIT
CRC0VAL
Write
Read
Figure 16.1. CRC0 Block Diagram
CRC0IN
CRC Engine
Rev. 1.0
8
8
RESULT
2 to 1 MUX
16
8
8
8
Automatic CRC
Controller
CRC0AUTO
CRC0DAT
CRC0CNT
Memory
Flash
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