C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 208

• Manufacturer Part Number: C8051F321-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel / 10 bit, 7 Channel
• Package: 28MLP
• Device Core: 8051
• Family Name: C8051F321
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F320/1
208
Master Mode Timing* (See Figure 18.8 and Figure 18.9)
T
T
T
T
Slave Mode Timing* (See Figure 18.10 and Figure 18.11)
T
T
T
T
T
T
T
T
T
T
*Note: T
MCKH
MCKL
MIS
MIH
SE
SD
SEZ
SDZ
CKH
CKL
SIS
SIH
SOH
SLH
Parameter
SYSCLK
is equal to one period of the device system clock (SYSCLK).
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
Table 18.1. SPI Slave Timing Parameters
Description
Rev. 1.4
1 x T
1 x T
1 x T
2 x T
2 x T
5 x T
5 x T
2 x T
2 x T
6 x T
SYSCLK
Min
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
—
SYSCLK
0
+ 20
4 x T
4 x T
4 x T
8 x T
Max
—
—
—
—
—
—
—
—
—
—
SYSCLK
SYSCLK
SYSCLK
SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns