C8051F321-GMR Silicon Laboratories Inc, C8051F321-GMR Datasheet - Page 99
C8051F321-GMR
Manufacturer Part Number
C8051F321-GMR
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Specifications of C8051F321-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F320DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel / 10 bit, 7 Channel
Package
28MLP
Device Core
8051
Family Name
C8051F321
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
For Use With
336-1480 - DAUGHTER CARD TOOLSTCK C8051F321336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F321-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “13. Oscillators” on page 116 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “20.3. Watchdog Timer Mode” on page 236 details the use of the Watchdog Timer). Pro-
gram execution begins at location 0x0000.
XTAL1
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Oscillator
Oscillator
Multiplier
External
Internal
Clock
Drive
Px.x
Px.x
System
Clock
Clock Select
Comparator 0
Figure 10.1. Reset Sources
+
-
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
VDD
WDT
PCA
EN
Rev. 1.4
Supply
Monitor
+
-
System Reset
Enable
Software Reset (SWRSF)
Power On
Reset
Operation
FLASH
Errant
Controller
'0'
USB
C8051F320/1
(wired-OR)
Transition
VBUS
Reset
Funnel
/RST
99
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