R5F21184SP#U0 Renesas Electronics America, R5F21184SP#U0 Datasheet - Page 271

• Manufacturer Part Number: R5F21184SP#U0
• Description: IC R8C MCU FLASH 16K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/18r

Specifications of R5F21184SP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x1b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• No. Of I/o's: 13
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 2.7V To 5.5V
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 5
5.2.4 Changing Interrupt Control Registers
(1) Individual interrupt control registers can only be modified while no interrupt requests corresponding
(2) When modifying an interrupt control register after disabling interrupts, care must be taken when
Changing Bits Other Than IR Bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR
bit may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. To get
around this problem, use the following instructions to modify the register: AND, OR, BCLR, BSET.
Changing IR Bit
Even when the IR bit is cleared to 0 (interrupt not requested), it may not actually be cleared to 0 depend-
ing on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0.
(3) When disabling interrupts using the I flag, refer to the following sample programs. (Refer to (2) above
Sample programs 1 to 3 are to prevent the I flag from being set to 1 (interrupt enabled) before writing to
the interrupt control registers depending on the state of the internal bus or the instruction queue buffer.
to that register are generated. If interrupt requests managed by the interrupt control register are
likely to occur, disable interrupts before changing the contents of the interrupt control register.
selecting the instructions to be used.
regarding changing interrupt control registers in the sample programs.)
Example 1: Use NOP instruction to prevent I flag being set to 1
Example 2: Use dummy read to delay FSET instruction
Example 3: Use POPC instruction to change I flag
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Interrupts
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
page 251 of 263
before interrupt control register is changed
I
#00H, 0056H ; Set TXIC register to 00
I
I
#00H, 0056H ; Set TXIC register to 00
I
I
#00H, 0056H ; Set TXIC register to 00
FLG
; Disable interrupts
; Enable interrupts
; Disable interrupts
; Dummy read
; Enable interrupts
; Disable interrupts
; Enable interrupts
16
16
16
5.2 Interrupt Control