C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 81

• Manufacturer Part Number: C8051F501-IQ
• Description: IC 8051 MCU 64K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F501-IQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1512

9.1. Comparator Multiplexer
C8051F50x/F51x devices include an analog input multiplexer for each of the comparators to connect Port
I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Def-
inition 9.5). The CMX0P3 – CMX0P0 bits select the Comparator0 positive input; the CMX0N3 – CMX0N0 bits
select the Comparator0 negative input. Similarly, the Comparator1 inputs are selected in the CPT1MX reg-
ister using the CMX1P3-CMX1P0 bits and CMX1N3-CMX1N0 bits. The same pins are available to both
multiplexers at the same time and can be used by both comparators simultaneously.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “20.6. Special Function Registers for Accessing
and Configuring Port I/O” on page 191).
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
P2.5
P2.7
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
Figure 9.3. Comparator Input Multiplexer Block Diagram
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
P2.4
P2.6
Rev. 1.2
CPn +
CPn -
C8051F50x/F51x
+
-
VDD
GND
81