C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 9
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C8051F501-IQ
Manufacturer Part Number
C8051F501-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F501-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1512
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F501-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F501-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F50x/F51x
Figure 13.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 105
Figure 13.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 106
Figure 15.1. Flash Program Memory Map ............................................................. 131
Figure 17.1. Reset Sources ................................................................................... 141
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 142
Figure 18.1. Multiplexed Configuration Example ................................................... 153
Figure 18.2. Non-multiplexed Configuration Example ........................................... 154
Figure 18.3. EMIF Operating Modes ..................................................................... 155
Figure 18.4. Non-multiplexed 16-bit MOVX Timing ............................................... 158
Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 159
Figure 18.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 160
Figure 18.7. Multiplexed 16-bit MOVX Timing ....................................................... 161
Figure 18.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 162
Figure 18.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 163
Figure 19.1. Oscillator Options .............................................................................. 165
Figure 19.2. Example Clock Multiplier Output ....................................................... 170
Figure 19.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 175
Figure 20.1. Port I/O Functional Block Diagram .................................................... 177
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 178
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 181
Figure 20.4. Crossbar Priority Decoder in Example Configuration ........................ 182
Figure 21.1. LIN Block Diagram ............................................................................ 201
Figure 22.1. Typical CAN Bus Configuration ......................................................... 218
Figure 22.2. CAN Controller Diagram .................................................................... 219
Figure 22.3. Four segments of a CAN Bit .............................................................. 221
Figure 23.1. SMBus Block Diagram ...................................................................... 226
Figure 23.2. Typical SMBus Configuration ............................................................ 227
Figure 23.3. SMBus Transaction ........................................................................... 228
Figure 23.4. Typical SMBus SCL Generation ........................................................ 230
Figure 23.5. Typical Master Write Sequence ........................................................ 237
Figure 23.6. Typical Master Read Sequence ........................................................ 238
Figure 23.7. Typical Slave Write Sequence .......................................................... 239
Figure 23.8. Typical Slave Read Sequence .......................................................... 240
Figure 24.1. UART0 Block Diagram ...................................................................... 243
Figure 24.2. UART0 Timing Without Parity or Extra Bit ......................................... 245
Figure 24.3. UART0 Timing With Parity ................................................................ 245
Figure 24.4. UART0 Timing With Extra Bit ............................................................ 245
Figure 24.5. Typical UART Interconnect Diagram ................................................. 246
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 247
Figure 25.1. SPI Block Diagram ............................................................................ 252
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 255
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ......................................................................... 255
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ......................................................................... 255
Rev. 1.2
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