R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 39
![IC R8C MCU FLASH 32LQFP](/photos/12/18/121815/r5f21134dfp_u0_sml.jpg)
R5F21134DFP#U0
Manufacturer Part Number
R5F21134DFP#U0
Description
IC R8C MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/13r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21132FPU0.pdf
(33 pages)
3.R5F21132FPU0.pdf
(226 pages)
4.R5F21134DFPU0.pdf
(224 pages)
Specifications of R5F21134DFP#U0
Core Size
16-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
R8C
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
22
Eeprom Memory Size
4KB
Ram Memory Size
1024Byte
Cpu Speed
20MHz
No. Of Timers
16
Digital Ic Case
RoHS Compliant
Controller Family/series
R8C/13
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21134DFP#U0R5F21134DFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- R5F211A2SPU0 PDF datasheet
- R5F21132FPU0 PDF datasheet #2
- R5F21132FPU0 PDF datasheet #3
- R5F21134DFPU0 PDF datasheet #4
- Current page: 39 of 300
- Download datasheet (2Mb)
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
1.10 Vector Tables
Chapter 1 Overview
Interrupt vector tables are the only vector tables. There are two types of interrupt vector tables: fixed and
variable.
Figure 1.10.1 Fixed Vector Table
1.10.1 Fixed Vector Tables
A fixed vector table is an address-fixed vector table. Part of the interrupt vector table is allocated to
addresses 0FFDC
Interrupt vector tables are composed of four bytes per table. Each vector table must contain the inter-
rupt handler routine’s entry address.
0FFDC
0FFFF
16
16
page 19 of 263
16
through 0FFFF
Interrupt
vector table
16
. Figure 1.10.1 shows a fixed vector table.
FFFDC
FFFE0
FFFE4
FFFE8
FFFEC
FFFF0
FFFF4
FFFF8
FFFFC
16
16
16
16
16
16
16
16
16
Oscillation stop detection/
watchdog timer
Undefined instruction
Overflow
BRK instruction
Address match
Single step
(Reserved)
(Reserved)
Reset
1.10 Vector Tables
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