R5F21254SDFP#U0 Renesas Electronics America, R5F21254SDFP#U0 Datasheet - Page 273
R5F21254SDFP#U0
Manufacturer Part Number
R5F21254SDFP#U0
Description
IC R8C MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21254SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21254SDFP#U0R5F21254SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Chapter 5
Figure 5.3.2 Interrupt Response Time
Table 5.3.1 Value of IPL when Software Interrupt and Special Interrupt Request Acknowledged
5.3.1 Interrupt Response Time
5.3.2 Changes of IPL when Interrupt Request Acknowledged
Interrupt Sources Without Interrupt Priority Levels
Watchdog timer, oscillation stop detection
Software, address-match, single-step
Figure 5.3.2 shows the interrupt response time. The interrupt response time is the period from when an
interrupt request is generated until the first instruction of the interrupt routine is executed. This period
consists of the time ((a) in Figure 5.3.1) from when the interrupt request is generated to when the
instruction then under way is completed and the time (20 cycles (b)) in which the interrupt sequence is
executed.
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in IPL.
When a software interrupt request or a special interrupt request is acknowledged, the value shown in
Table 5.3.1 is set in IPL. Table 5.3.1 shows the value of IPL when software interrupts and special
interrupt requests are acknowledged.
(a) Time from when interrupt request is generated to when the instruction then under execution is
(b) The address-match interrupt and the single-step interrupt are each 21 cycles.
Interrupt request generated
completed. Time (a) varies with the instruction being executed. The DIVX instruction requires a
maximum time of 30 cycles (cycle number: no wait states, divisor is stored in a register).
Interrupts
page 253 of 263
Instruction
Interrupt response time
(a)
Interrupt request acknowledged
Interrupt sequence
20 cycles (b)
Instruction in interrupt
routine
Value that is set to IPL
Not changed
7
5.3 Interrupt Sequence
Time
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