C8051F410-GQ Silicon Laboratories Inc, C8051F410-GQ Datasheet - Page 73

• Manufacturer Part Number: C8051F410-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F41xr

Specifications of C8051F410-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 20x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2368 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 24
• Ram Memory Size: 2368Byte
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1453 - ADAPTER PROGRAM TOOLSTICK F410336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1318

6.3.
The IDA0 output is connected to P0.0, and the IDA1 output can be connected to P0.0 or P0.1. The output
pin for IDA1 is selected using IDAMRG (REF0CN.7). When the enable bits for both IDACs (IDAnEN) are
set to ‘0’, the IDAC outputs behave as a normal GPIO pins. When either IDAC’s enable bit is set to ‘1’, the
digital output drivers and weak pullup for the selected IDAC pin are automatically disabled, and the pin is
connected to the IDAC output. When using the IDACs, the selected IDAC pin(s) should be skipped in the
Crossbar by setting the corresponding PnSKIP bits to a ‘1’. Figure 6.3 shows the pin connections for IDA0
and IDA1.
When both IDACs are enabled and IDAMRG is set to logic 1, the output of both IDACs is merged onto
P0.0.
Bits 7–0: IDA1 Data Word High-Order Bits.
Bits 7–0: IDA1 Data Word Low-Order Bits.
R/W
R/W
Bit7
Bit7
IDAC External Pin Connections
For IDA0RJST = 0:
Bits 7-0 hold the most significant 8-bits of the 12-bit IDA1 Data Word.
For IDA0RJST = 1:
Bits 3-0 hold the most significant 4-bits of the 12-bit IDA1 Data Word. Bits 7–4 are 0000b.
For IDA0RJST = 0:
Bits 7-4 hold the least significant 4-bits of the 12-bit IDA1 Data Word. Bits 3–0 are 0000b.
For IDA0RJST = 1:
Bits 7–0 hold the least significant 8-bits of the 12-bit IDA1 Data Word.
R/W
R/W
Bit6
Bit6
SFR Definition 6.5. IDA1H: IDA0 Data High Byte
SFR Definition 6.6. IDA1L: IDA1 Data Low Byte
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.1
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
C8051F410/1/2/3
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
R/W
R/W
Bit0
Bit0
0xF5
0xF4
00000000
00000000
Reset Value
Reset Value
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