C8051F361-GQ Silicon Laboratories Inc, C8051F361-GQ Datasheet - Page 102

• Manufacturer Part Number: C8051F361-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F361-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1408

C8051F360/1/2/3/4/5/6/7/8/9
9.4.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic ‘1’. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic ‘0’, selecting the feature's default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-
sponding system function.
102
Bits 7–0: SP: Stack Pointer.
Bits 7–0: DPL: Data Pointer Low.
Bits 7–0: DPH: Data Pointer High.
SFR Page:
SFR Address:
SFR Page
SFR Address:
SFR Page:
SFR Address:
R/W
R/W
R/W
Bit7
Bit7
Bit7
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
all pages
0x81
all pages
0x82
all pages
0x83
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 9.7. DPH: Data Pointer High Byte
SFR Definition 9.6. DPL: Data Pointer Low Byte
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 9.5. SP: Stack Pointer
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.0
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
00000000
00000000
Reset Value
00000111
Reset Value
Reset Value