MC9S12C32CFUE16 Freescale Semiconductor, MC9S12C32CFUE16 Datasheet - Page 116

• Manufacturer Part Number: MC9S12C32CFUE16
• Description: IC MCU 32K FLASH 16MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFUE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3 Module Mapping Control (MMCV4) Block Description
3.3.2.4
Read: Anytime
Write: As stated in each bit description
This register initializes miscellaneous control functions.
116
Module Base + 0x0013
Starting address location affected by INITRG register setting.
1. The reset state of this bit is determined at the chip integration level.
EXSTR[1:0]
Reset: Special Test
ROMHM
ROMON
Reset: Expanded
Reset: Peripheral
Field
3:2
or Single Chip
1
0
or Emulation
External Access Stretch Bits 1 and 0
Write: once in normal and emulation modes and anytime in special modes
This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in
Table
FLASH EEPROM or ROM Only in Second Half of Memory Map
Write: once in normal and emulation modes and anytime in special modes
0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed.
1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical
ROMON — Enable FLASH EEPROM or ROM
Write: once in normal and emulation modes and anytime in special modes
This bit is used to enable the FLASH EEPROM or ROM memory in the memory map.
0 Disables the FLASH EEPROM or ROM from the memory map.
1 Enables the FLASH EEPROM or ROM in the memory map.
Miscellaneous System Control Register (MISC)
locations of the FLASH EEPROM or ROM remain accessible through the program page window.
Writes to this register take one cycle to go into effect.
W
R
3-6. In single chip and peripheral modes these bits have no meaning or effect.
0
0
0
0
7
Figure 3-6. Miscellaneous System Control Register (MISC)
= Unimplemented or Reserved
0
0
0
0
6
Table 3-5. INITEE Field Descriptions
MC9S12C-Family / MC9S12GC-Family
0
0
0
0
5
Rev 01.24
NOTE
Description
0
0
0
0
4
EXSTR1
1
1
1
3
EXSTR0
1
1
1
2
Freescale Semiconductor
ROMHM
0
0
0
1
ROMON
—
0
1
0
1