MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 212
MC908AZ60ACFUER
Manufacturer Part Number
MC908AZ60ACFUER
Description
IC MCU 60K FLASH 8.4MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFUER
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08AZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8.4 MHz
Number Of Programmable I/os
52
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 15 Channel
Controller Family/series
HC08
No. Of I/o's
52
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC908AZ60ACFUERTR
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC908AZ60ACFUER
Manufacturer:
FREESCALE
Quantity:
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Part Number:
MC908AZ60ACFUER
Manufacturer:
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Serial Peripheral Interface (SPI)
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
212
SCK CYCLE
NUMBER
CPHA = 1
CPHA = 0
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
SCK
SCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
BUS
BUS
BUS
BUS
BUS
MOSI
TO SPDR
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
WRITE
Figure 19-6. Transmission Start Delay (Master)
TO SPDR
WRITE
EARLIEST LATEST
EARLIEST
EARLIEST
EARLIEST
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
SCK = INTERNAL CLOCK ÷ 128;
INITIATION DELAY
SCK = INTERNAL CLOCK ÷ 32;
128 POSSIBLE START POINTS
SCK = INTERNAL CLOCK ÷ 2;
SCK = INTERNAL CLOCK ÷ 8;
32 POSSIBLE START POINTS
2 POSSIBLE START POINTS
8 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
BIT 5
3
Freescale Semiconductor
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