HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 66
HD64F3664FPV
Manufacturer Part Number
HD64F3664FPV
Description
IC H8/3664 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3664FPV
Core Size
16-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300H
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
No. Of I/o's
29
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
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HD64F3664FPV
Manufacturer:
MURATA
Quantity:
34 000
Company:
Part Number:
HD64F3664FPV
Manufacturer:
HD
Quantity:
465
Company:
Part Number:
HD64F3664FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664FPV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 2 CPU
(1)
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
(2)
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4)
(a)
The register field of the instruction code specifies an address register (ERn) the lower 24 bits of
which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added
to the address register contents (32 bits) and the sum is stored in the address register. The value
added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword
access, the register value should be even.
(b) Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in
the instruction code, and the lower 24 bits of the result is the address of a memory operand. The
result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access. For the word or longword access, the register value should be
even.
Rev. 6.00 Mar. 24, 2006 Page 36 of 412
REJ09B0142-0600
Register Direct—Rn
Register Indirect—@ERn
Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register indirect with post-increment—@ERn+
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