C8051F007-GQ Silicon Laboratories Inc, C8051F007-GQ Datasheet - Page 21

• Manufacturer Part Number: C8051F007-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F00xr

Specifications of C8051F007-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F0xx
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1188 - DEV KIT FOR F005/006/007
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1190

4. PINOUT AND PACKAGE DEFINITIONS
21
VDD
DGND
AV+
AGND
TCK
TMS
TDI
TDO
XTAL1
XTAL2
/RST
VREF
CP0+
CP0-
CP1+
CP1-
DAC0
DAC1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Name
F000
F005
F010
F015
31,
40,
30,
41,
16,
62
61
17
15
22
21
28
29
18
19
20
64
63
10
11
12
5,
6
4
3
2
1
7
8
9
Pin Numbers
F001
F006
F011
F016
23,
22,
33,
27,
13,
44,
32
19
43
12
18
17
20
21
14
15
16
45
46
48
47
3
2
1
4
5
6
7
8
9
F002
F007
F012
F017
18,
17,
20
21
29
30
14
13
15
16
10
11
12
32
31
9,
8,
3
2
1
4
5
6
7
D In
D In
D In
D Out
A In
A Out
D I/O
A I/O
A In
A In
A In
A In
A Out
A Out
A In
A In
A In
A In
A In
A In
Type
Table 4.1. Pin Definitions
Description
Digital Voltage Supply.
Digital Ground.
Positive Analog Voltage Supply.
Analog Ground.
JTAG Test Clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of
TCK.
JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on
the falling edge of TCK. TDO output is a tri-state driver.
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V. An external source can force a system reset by
driving this pin low.
Voltage Reference. When configured as an input, this pin is the voltage
reference for the MCU. Otherwise, the internal reference drives this pin.
Comparator 0 Non-Inverting Input.
Comparator 0 Inverting Input.
Comparator 1 Non-Inverting Input.
Comparator 1 Inverting Input.
Digital to Analog Converter Output 0. The DAC0 voltage output. (See
Section 7 DAC Specification for complete description).
Digital to Analog Converter Output 1. The DAC1 voltage output. (See
Section 7 DAC Specification for complete description).
Analog Mux Channel Input 0. (See ADC Specification for complete
description).
Analog Mux Channel Input 1. (See ADC Specification for complete
description).
Analog Mux Channel Input 2. (See ADC Specification for complete
description).
Analog Mux Channel Input 3. (See ADC Specification for complete
description).
Analog Mux Channel Input 4. (See ADC Specification for complete
description).
Analog Mux Channel Input 5. (See ADC Specification for complete
description).
Rev. 1.7