C8051F007-GQ Silicon Laboratories Inc, C8051F007-GQ Datasheet - Page 74

• Manufacturer Part Number: C8051F007-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F00xr

Specifications of C8051F007-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F0xx
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1188 - DEV KIT FOR F005/006/007
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1190

10.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should
not be set to logic l. Future product versions may use these bits to implement new features in which case the reset
value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are
included in the sections of the datasheet associated with their corresponding system function.
Bits 7-0: SP: Stack Pointer.
Bits 7-0: DPL: Data Pointer Low.
Bits 7-0: DPH: Data Pointer High.
R/W
R/W
R/W
Bit7
Bit7
Bit7
The stack pointer holds the location of the top of the stack. The stack pointer is
incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 10.5. DPH: Data Pointer High Byte
Figure 10.4. DPL: Data Pointer Low Byte
R/W
R/W
R/W
Bit5
Bit5
Bit5
Figure 10.3. SP: Stack Pointer
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.7
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
Reset Value
Reset Value
Reset Value
00000111
00000000
00000000
0x81
0x82
0x83
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