C8051F060-GQ Silicon Laboratories Inc, C8051F060-GQ Datasheet - Page 75

• Manufacturer Part Number: C8051F060-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F060-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1214 - DEV KIT FOR F060/F062/F063
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1213

6.
The DMA interface works in conjunction with ADC0 and ADC1 to write ADC outputs directly to a specified
region of XRAM. The DMA interface is configured by software using the Special Function Registers shown
in Figure 6.1. Up to 64 instructions can be programmed into the Instruction Buffer to designate a sequence
of DMA operations. The Instruction Buffer is accessed by the DMA Control Logic, which gathers the appro-
priate data from the ADCs and controls writes to XRAM. The DMA instructions tell the DMA Control Logic
which ADC(s) to expect results from, but do not initiate the actual conversions. It is important to configure
the ADCs for the desired start-of-conversion source, voltage reference, and SAR clock frequency prior to
starting the DMA interface. For information on setting up the ADCs, refer to
and ADC1)” on page
6.1.
The Instruction Buffer has 64 8-bit locations that can be programmed with a sequence of DMA instructions.
Filling the Instruction Buffer is done with the Special Function Registers DMA0IPT (DMA Instruction Write
Address Register, Figure 6.6) and DMA0IDT (DMA Instruction Write Data Register, Figure 6.7). Instruc-
tions are written to the Instruction Buffer at address DMA0IPT when the instruction word is written to
DMA0IDT. Reading the register DMA0IDT will return the instruction word at location DMA0IPT. After a write
or read operation on DMA0IDT, the DMA0IPT register is automatically incremented to the next Instruction
Buffer location.
Direct Memory Access Interface (DMA0)
Writing to the Instruction Buffer
AIN0G
AIN1G
Current Address
Start Address
AIN0
AIN1
DMA0BND
DMA0ISW
DMA0IPT
Address
51.
ADC0
ADC1
Instruction
(64 Bytes)
Write Logic
Buffer
Instruction Data
DMA0IDT
DMA0CTH
Figure 6.1. DMA0 Block Diagram
Repeat Counter Limit
DMA0CTL
Rev. 1.2
DMA0CF
Control Logic
C8051F060/1/2/3/4/5/6/7
DMA
DMA0CSH
DMA0CN
Current Repeat Counter Value
DMA0DSH
DMA0DAH
Address Bus
Data Bus
Section “5. 16-Bit ADCs (ADC0
Beginning XRAM Address
Current XRAM Address
DMA0CSL
(on-chip or
off-chip)
DMA0DSL
DMA0DAL
XRAM
75