M3087BFLGP#U3 Renesas Electronics America, M3087BFLGP#U3 Datasheet - Page 25
M3087BFLGP#U3
Manufacturer Part Number
M3087BFLGP#U3
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M3087BFLGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
1.4 Flag Register (FLG)
e
E
v
J
Chapter 1 Overview
Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below.
1 .
0
(1) Bit 0: Carry Flag (C flag)
(2) Bit 1: Debug Flag (D flag)
(3) Bit 2: Zero Flag (Z flag)
(4) Bit 3: Sign Flag (S flag)
(5) Bit 4: Register Bank Select Flag (B flag)
(6) Bit 5: Overflow Flag (O flag)
(7) Bit 6: Interrupt Enable Flag (I flag)
(8) Bit 7: Stack Pointer Select Flag (U flag)
(9) Bits 8-11: Reserved Area
9
0 .
B
This flag holds a carry, borrow, or shifted-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is set (= 1), a single-step interrupt is generated after an instruction is executed. When
an interrupt is acknowledged, this flag is cleared to 0.
This flag is set when an arithmetic operation resulted in 0; otherwise, this flag is 0.
This flag is set when an arithmetic operation resulted in a negative value; otherwise, this flag is 0.
This flag selects a register bank. If this flag is 0, register bank 0 is selected; when the flag is 1,
register bank 1 is selected.
This flag is set when an arithmetic operation resulted in overflow.
This flag enables a maskable interrupt.
When this flag is 0, the interrupt is disabled; when the flag is 1, the interrupt is enabled. When the
interrupt is acknowledged, this flag is cleared to 0.
When this flag is 0, the interrupt stack pointer (ISP) is selected; when the flag is 1, the user stack
pointer (USP) is selected.
This flag is cleared to 0 when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
0
0
3
1
2
9
0
0 -
0
6
1
0 .
0
0
5
3 .
1
p
a
g
e
7
f o
3
3
5
1.4 Flag Register (FLG)
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