MC9S12XDT512CAA Freescale Semiconductor, MC9S12XDT512CAA Datasheet - Page 1103
MC9S12XDT512CAA
Manufacturer Part Number
MC9S12XDT512CAA
Description
IC MCU 512K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDT512CAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12XDT512CAAR
Manufacturer:
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26.6.1
Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased
using the following method :
After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the
Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM
will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM
status register. This BDM action will cause the MCU to override the Flash security state and the MCU will
be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state.
26.7
26.7.1
On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the
EPROT register from the EEPROM memory according to
26.7.2
If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted.
The state of a word being programmed or the sector / block being erased is not guaranteed.
26.8
The EEPROM module can generate an interrupt when all EEPROM command operations have completed,
when the EEPROM address, data, and command buffers are empty.
Freescale Semiconductor
EEPROM address, data, and command buffers empty
All EEPROM commands completed
•
Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a
mass erase command write sequence to erase the EEPROM memory.
Resets
Interrupts
Unsecuring the MCU in Special Single Chip Mode using BDM
EEPROM Reset Sequence
Reset While EEPROM Command Active
Vector addresses and their relative interrupt priority are determined at the
MCU level.
Interrupt Source
Table 26-11. EEPROM Interrupt Sources
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
(ESTAT register)
(ESTAT register)
Interrupt Flag
CBEIF
CCIF
Table
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
26-1.
(ECNFG register)
(ECNFG register)
Local Enable
CBEIE
CCIE
Global (CCR) Mask
I Bit
I Bit
1105
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