MC9S12XEP100MAG Freescale Semiconductor, MC9S12XEP100MAG Datasheet - Page 384

IC MCU 16BIT 1M FLASH 144-LQFP

MC9S12XEP100MAG

Manufacturer Part Number
MC9S12XEP100MAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100MAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10 XGATE (S12XGATEV3)
10.8
10.8.1
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all
operations must have one of the eight general purpose registers R0 … R7 as their source as well their
destination.
All word accesses must work with a word aligned address, that is A[0] = 0!
10.8.1.1
10.8.1.2
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE
registers.
Examples:
384
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
RD
RD.L
RD.H
RS, RS1, RS2
RS.L, RS1.L, RS2.L
RS.H, RS1.H, RS2.H
RB
RI
RI+
–RI
Instruction Set
BRK
RTS
Addressing Modes
Naming Conventions
Inherent Addressing Mode (INH)
Even though register R1 is intended to be used as a pointer to the data
segment, it may be used as a general purpose data register as well.
Selecting R0 as destination register will discard the result of the instruction.
Only the condition code register will be updated
MC9S12XE-Family Reference Manual , Rev. 1.23
Destination register, allowed range is R0–R7
Low byte of the destination register, bits [7:0]
High byte of the destination register, bits [15:8]
Source register, allowed range is R0–R7
Low byte of the source register, bits [7:0]
High byte of the source register, bits[15:8]
Base register for indexed addressing modes, allowed
range is R0–R7
Offset register for indexed addressing modes with
register offset, allowed range is R0–R7
Offset register for indexed addressing modes with
register offset and post-increment,
Allowed range is R0–R7 (R0+ is equivalent to R0)
Offset register for indexed addressing modes with
register offset and pre-decrement,
Allowed range is R0–R7 (–R0 is equivalent to R0)
NOTE
Freescale Semiconductor

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