M30626FHPGP#U7C Renesas Electronics America, M30626FHPGP#U7C Datasheet - Page 130

• Manufacturer Part Number: M30626FHPGP#U7C
• Description: IC M16C MCU FLASH 384K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FHPGP#U7C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/IEBus/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• Cpu Family: M16C
• Device Core Size: 16/32Bit
• Frequency (max): 24MHz
• Total Internal Ram Size: 31KB
• # I/os (max): 87
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 12.3 Settings of Interrupt Priority Levels
12.5.1
12.5.2
12.5.3
ILVL2 to ILVL0 Bits
000b
001b
010b
011b
100b
101b
110b
111b
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable
interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (=
interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 12.3 shows the Settings of Interrupt Priority Levels and Table 12.4 shows the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is accepted:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
•
•
•
Jan 10, 2006
I flag = 1
IR bit = 1
interrupt priority level > IPL
I Flag
IR Bit
ILVL2 to ILVL0 Bits and IPL
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority
Page 113 of 390
Level
Priority
Order
High
Low
−
Table 12.4Interrupt Priority Levels Enabled by IPL
000b
001b
010b
011b
100b
101b
110b
111b
IPL
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Enabled Interrupt Priority Levels
12. Interrupt