DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 9
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Item
2.6 Number of States
Required for Instruction
Execution
Table 2.5 Number of
Cycles in Instruction
Execution
2.7 Bus States During
Instruction Execution
Table 2.6 Instruction
Execution Cycles
3.3.5 Usage Notes
Page
283,
285,
286,
288
290
293 to
302
312,
313
Revisions (See Manual for Details)
Note 6 added
Notes: 6. The number of states may differ depending on the
product. For details, refer to the hardware manual of the
product in question.
:M deleted from legend
All instances of :M deleted from table
Newly added
Instruction
CLRMAC *
Instruction
LDMAC *
Instruction
MULXS
MULXU
Instruction
STMAC *
5
5
5
MULXU.B Rs,Rd
Mnemonic
CLRMAC
Mnemonic
LDMAC ERs,MACH
LDMAC ERs,MACL
Mnemonic
MULXS.B Rs,Rd
MULXS.W Rs,ERd H8S/2600
MULXU.W Rs,ERd H8S/2600
Mnemonic
STMAC MACH,ERd
STMAC MACL,ERd
H8S/2600
H8S/2000
H8S/2000
H8S/2600
H8S/2000
H8S/2000
Instruction
Fetch
I
1
Instruction
Fetch
I
1
1
Instruction
Fetch
I
2
2
2
2
1
1
1
1
Instruction
Fetch
I
1
1
Rev. 4.00 Feb 24, 2006 page vii of xiv
1
1
1
Branch
Address
Read
J
Branch
Address
Read
J
Branch
Address
Read
J
2
1
3
1
2
1
3
1
Branch
Address
Read
J
Stack
Operation
Stack
Operation
Stack
Operation
Stack
Operation
K
K
K
K
Byte Data
Access
L
Byte Data
Access
L
Byte Data
Access
L
Byte Data
Access
L
Word Data
Access
M
Word Data
Access
M
Word Data
Access
M
Word Data
Access
M
Internal
Operation
N
Internal
Operation
N
Internal
Operation
N
Internal
Operation
N
0 *
0 *
*
*
*
*
1
*
9
*
1
*
9
3
3
3
3
3
3
3
3
3
*
*
*
*
*
*
*
*
*
6
6
6
6
6
6
6
6
6
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