MC9S12DG256
Target Applications
> Automotive applications
> Industrial control
Overview
Freescale Semiconductor’s HCS12 Family of
microcontrollers (MCUs) is the next generation of
the highly successful 68HC12 architecture. Using
Freescale’s industry-leading 0.25 µs Flash, the
MC9S12DG256 is part of a pin-compatible
family that scales from 32 KB to 512 KB of Flash
memory. The MC9S12DG256 provides an upward
migration path from Freescale’s 68HC08, 68HC11
and 68HC12 architectures for applications that
need larger memory, more peripherals and higher
performance. Also, with the increasing number of
CAN-based electronic control units (ECUs), its
multiple network modules support this environment
by enabling highly efficient communications
between different network buses.
16-bit Microcontrollers
16-Key Wake-Up
3 x SPI
5V to 2.5V
IRQ Ports
2 x CAN
2 x SCI
2.0 A/B
Vreg
I
2
C
HCS12 CPU
10-bit, 8-ch.
12 KB RAM
ATD0
Enhanced Capture Timer
8-bit, 8 ch./16-bit, 4-ch.
256 KB Flash
16-bit, 8-ch.
PWM
4 KB EEPROM
10-bit, 8-ch.
ATD1
On-Chip Debug Interface
Features
High-Performance 16-bit HCS12 CPU Core
> 25 MHz bus operation at 5V for 40 ns
> Dedicated serial debug interface
> On-chip breakpoints
Network Modules
> Two msCAN modules implementing the CAN
Integrated Third-Generation Flash Memory
> In-application reprogrammable
> Self-timed, fast programming
> 5V Flash program/erase/read
> Flash granularity—512 byte Flash
> Four independently programmable
> Flexible block protection and security
4 KB Integrated EEPROM
> Flexible protection scheme for protection
> EEPROM can be programmed in 46 µs
• Five receive buffers per module with FIFO
• Three transmit buffers per module with
• Fast Flash page erase—20 ms
• Can program 16 bits in 20 µs while
minimum instruction cycle time
2.0 A/B protocol
erase/2 byte Flash program
Flash arrays
against accidental program or erase
storage scheme
internal prioritization
(512 bytes)
in burst mode
> Opcode compatible with the 68HC11
> C-optimized architecture produces extremely
> Real-time in-circuit emulation and debug
> Read/write memory and registers while running
> Ability to link modules for higher
> Programmable bit rate up to 1 Mbps
> FIFO receive approach superior for
> Flexibility to change code in the field
> Efficient end-of-line programming
> Total program time for 256 KB code is less
> Reduces production programming cost
> No external high voltage or charge
> Virtual EEPROM implementation, Flash array
> Can erase one array while executing code
> Can erase 4 bytes at a time and program
Benefits
and 68HC12
compact code
without expensive and cumbersome
box emulators
at full speed
buffer count
event-driven networks
than 10 seconds
through ultra-fast programming
pump required
usable for EE extension
from another
2 bytes at a time for calibration, security,
personality and diagnostic information