SAF-XC164TM-4F40F AA Infineon Technologies, SAF-XC164TM-4F40F AA Datasheet - Page 40

• Manufacturer Part Number: SAF-XC164TM-4F40F AA
• Description: IC MCU 16BIT 32KB TQFP-64-8
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164TM-4F40F AA

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Packages: PG-LQFP-64
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 4.0 KByte
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 32.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: FX164TM4F40FAAXT; SAF-XC164TM-4F40FAA; SAF-XC164TM-4F40FAAINTR; SAF-XC164TM-4F40FAATR; SAF-XC164TM-4F40FAATR; SAFXC164TM4F40FAAXT; SP000105871

XC164TM
Derivatives
Functional Description
3.12
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
f
to generate the clock signals for the XC164TM with high flexibility. The master clock
MC
f
is the reference clock signal and is output to the external system. The CPU clock
CPU
f
and the system clock
are derived from the master clock either directly (1:1) or via a
SYS
f
f
f
2:1 prescaler (
=
=
/ 2). See also
Section
4.4.1.
SYS
CPU
MC
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Data Sheet
38
V1.2, 2007-03