SAF-XC164CM-4F40F AA Infineon Technologies, SAF-XC164CM-4F40F AA Datasheet - Page 62
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SAF-XC164CM-4F40F AA
Manufacturer Part Number
SAF-XC164CM-4F40F AA
Description
IC MCU 16BIT FLASH TQFP-64-8
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC164CM-4F20F_AA.pdf
(70 pages)
Specifications of SAF-XC164CM-4F40F AA
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
47
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 14x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
2xASC, 2xSSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
47
Number Of Timers
9
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
For Use With
B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CMMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FX164CM4F40FAAXT
SAF-XC164CM-4F40FAA
SAF-XC164CM-4F40FAAINTR
SAF-XC164CM-4F40FAATR
SAF-XC164CM-4F40FAATR
SAFXC164CM4F40FAAXT
SP000084410
SAF-XC164CM-4F40FAA
SAF-XC164CM-4F40FAAINTR
SAF-XC164CM-4F40FAATR
SAF-XC164CM-4F40FAATR
SAFXC164CM4F40FAAXT
SP000084410
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
frequency as the CPU clock signal
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of
directly follows the frequency of
cycle of the input clock
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
is locked to
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and
Data Sheet
MC
MC
MC
, the timing must be calculated using the minimum TCP possible under the respective
=
=
f
CPU
f
f
OSC
OSC
f
=
MC
/ ((PLLIDIV + 1) × (PLLODIV + 1)).
/ ((3 + 1) × (14 + 1)) =
f
f
MC
OSC
=
f
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
OSC
. The slight variation causes a jitter of
× F) which results from the input divider, the multiplication factor, and
f
OSC
.
f
OSC
f
OSC
f
CPU
so the high and low time of
Figure
/ 60.
f
CPU
.
60
=
16).
f
MC
) or can be the master clock divided by
B
) the on-chip phase locked loop is
B
f
f
MC
CPU
) the master clock is derived from
which also affects the duration
f
. The CPU clock can have the
MC
is constantly adjusted so it
f
f
MC
SYS
Electrical Parameters
is defined by the duty
which has the same
f
CPU
is derived from
Derivatives
V1.4, 2007-03
XC164CM
f
MC