SAF-C161PI-L25M CA Infineon Technologies, SAF-C161PI-L25M CA Datasheet - Page 67
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SAF-C161PI-L25M CA
Manufacturer Part Number
SAF-C161PI-L25M CA
Description
IC MCU 16BIT ROM/LESS MQFP-100-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161PI-LM_CA.pdf
(82 pages)
Specifications of SAF-C161PI-L25M CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-SQFP
Data Bus Width
16 bit
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-MQFP-100
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
F161PIL25MCAXT
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
SAF-C161PI-L25MCA
SAF-C161PI-L25MCAINTR
SAF-C161PI-L25MCATR
SAF-C161PI-L25MCATR
SAFC161PIL25MCAXT
SP000014368
Demultiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data hold after WR
ALE rising edge after RD,
WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to
RdCS, WrCS (with RW-
delay)
ALE falling edge to
RdCS, WrCS (no RW-
delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Data Sheet
1)
1)
3)
2)
3)
3)
Symbol
24
26
28
38
39
41
42
43
46
47
48
49
50
51
53
68
A
+
CC 10 +
CC -10 +
CC 0 +
CC -4 -
CC 6 +
CC 16 +
CC -4 +
CC 30 +
CC 50 +
CC 26 +
SR –
SR –
SR –
SR 0
SR –
SR –
C
+
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
min.
= 25 MHz
F
F
A
A
65
F
A
C
C
C
F
–
–
–
10 -
40 +
–
–
–
16 +
36 +
–
–
–
–
20 +
0 +
C
max.
+ 2
F
A
C
C
F
A
1 / 2TCL = 1 to 25 MHz
TCL - 10
+
-10 +
0 +
-4 -
–
TCL - 14
+
TCL - 4
+
-4
+
–
–
2TCL - 10
+
3TCL - 10
+
2TCL - 14
+
0
–
–
Variable CPU Clock
F
F
A
A
C
C
C
min.
F
A
F
–
–
–
10 -
3TCL - 20
+
–
–
–
2TCL - 24
+
3TCL - 24
+
–
–
–
–
2TCL - 20
+ 2
TCL - 20
+ 2
C
C
C
max.
A
A
+ 2
A
+
+
F
F
A
&3,
1)
1)
1999-07
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns