MC908AZ60AVFUR2 Freescale Semiconductor, MC908AZ60AVFUR2 Datasheet - Page 331

• Manufacturer Part Number: MC908AZ60AVFUR2
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUR2

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC908AZ60AVFUR2TR

26.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
ADCO — ADC Continuous Conversion Bit
ADCH[4:0] — ADC Channel Select Bits
Freescale Semiconductor
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC
interrupt request. Reset clears this bit.
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 15 ADC
channels. Channel selection is detailed in the following table. Care should be taken when using a port
pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the
analog signal. See
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets these bits.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
1 = Continuous ADC conversion
0 = One ADC conversion
CPU interrupt enabled (AIEN = 1)
Address:
Recovery from the disabled state requires one conversion cycle to stabilize.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
or
Table
Figure 26-2. ADC Status and Control Register (ADSCR)
COCO
$0038
Bit 7
R
R
0
26-1.
= Reserved
AIEN
6
0
ADCO
5
0
NOTE
CH4
4
1
CH3
3
1
CH2
2
1
CH1
1
1
Bit 0
CH0
1
I/O Registers
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