SAK-XC164CM-4F40F AA Infineon Technologies, SAK-XC164CM-4F40F AA Datasheet - Page 65
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SAK-XC164CM-4F40F AA
Manufacturer Part Number
SAK-XC164CM-4F40F AA
Description
IC MCU 16BIT 32KB FLSH TQFP-64-8
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC164CM-4F20F_AA.pdf
(70 pages)
Specifications of SAK-XC164CM-4F40F AA
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
47
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 14x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFP
For Use With
B158-H8961-X-X-7600IN - KIT EASY XC164CMXC164CMUCANIN - KIT U-CAN STARTER XC164CMMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SAK-XC164CM-4F40FAACT
SAK-XC164CM-4F40FAACT
SAK-XC164CM-4F40FAAINCT
SAK-XC164CM-4F40FAACT
SAK-XC164CM-4F40FAAINCT
4.4.2
The XC164CM’s Flash module delivers data within a fixed access time (see
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
frequency.
The Flash access waitstates only affect non-sequential accesses. Due to prefetching
mechanisms, the performance for sequential accesses (depending on the software
structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average performance by
5% … 15%.
Table 17
Parameter
Flash module access time
Programming time per 128-byte block
Erase time per sector
1) The actual access time is influenced by the system frequency, see
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18
Table 18
Required Waitstates
0 WS (WSFLASH = 00
1 WS (WSFLASH = 01
Note: The maximum achievable system frequency is limited by the properties of the
Data Sheet
t
ACC
respective derivative, i.e. 40 MHz (or 20 MHz for XC164CM-xF20F devices).
of the Flash array. The required Flash waitstates depend on the actual system
indicates the interrelation of waitstates and system frequency.
On-chip Flash Operation
Flash Characteristics (Operating Conditions apply)
Flash Access Waitstates
B
B
)
)
Symbol
t
t
t
ACC
PR
ER
Frequency Range
f
f
CPU
CPU
63
≤ 20 MHz
≤ 40 MHz
CC –
CC –
CC –
Min.
Table
Limit Values
18.
Typ.
–
2
200
2)
Electrical Parameters
2)
Max.
50
5
500
1)
Derivatives
V1.4, 2007-03
XC164CM
Table
Unit
ns
ms
ms
17).