PIC12F615-I/MD Microchip Technology, PIC12F615-I/MD Datasheet - Page 107

• Manufacturer Part Number: PIC12F615-I/MD
• Description: IC PIC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F615-I/MD

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Digital Ic Case Style: DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 11-8:
TABLE 11-7:
© 2006 Microchip Technology Inc.
INTCON
IOC
PIR1
PIE1
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
INSTRUCTION FLOW
Name
Note 1: PIC12F615/HV615 only.
GIE bit
(INTCON reg.)
INTF flag
(INTCON reg.)
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
Shaded cells are not used by the interrupt module.
Bit 7
GIE
(3)
—
—
—
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Q1
ADIF
ADIE
Bit 6
PEIE
Inst (PC – 1)
Inst (PC)
—
INT PIN INTERRUPT TIMING
(1)
Q2
PC
(1)
(1)
Q3 Q4
(4)
CCP1IF
CCP1IE
IOC5
Bit 5
T0IE
(5)
(1)
(1)
Q1
Inst (PC + 1)
Inst (PC)
IOC4
Bit 4
INTE
Q2
(1)
—
—
PIC12F609/615/12HV609/615
PC + 1
Q3 Q4
CY
. Synchronous latency = 3 T
CMIE
Preliminary
GPIE
IOC3
CMIF
Bit 3
Interrupt Latency
Q1
IOC2
Bit 2
T0IF
Dummy Cycle
—
—
Q2
PC + 1
—
Q3 Q4
TMR2IF
TMR2IE
Section 15.0 “Electrical Specifications”
IOC1
INTF
Bit 1
(2)
CY
, where T
(1)
(1)
Q1
Dummy Cycle
Inst (0004h)
TMR1IE -00- 0-00 -000 0-00
TMR1IF -00- 0-00 -000 0-00
Q2
GPIF
IOC0
Bit 0
0004h
CY
= instruction cycle time. Latency
Q3 Q4
0000 0000 0000 0000
--00 0000 --00 0000
POR, BOR
Value on
Q1
DS41302A-page 105
.
Inst (0005h)
Q2
Inst (0004h)
0005h
Value on
all other
Q3 Q4
Resets