PIC12F615-I/MD Microchip Technology, PIC12F615-I/MD Datasheet - Page 14
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PIC12F615-I/MD
Manufacturer Part Number
PIC12F615-I/MD
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-ESN.pdf
(168 pages)
Specifications of PIC12F615-I/MD
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
3
Digital Ic Case Style
DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F615-ESN PDF datasheet #4
- Current page: 14 of 168
- Download datasheet (3Mb)
PIC12F609/615/12HV609/615
TABLE 2-2:
DS41302A-page 12
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note
Addr
1:
INDF
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
VRCON
CMCON0
CMCON1
ADRESH
ADCON0
Name
—
—
—
—
—
—
—
—
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Unimplemented
Unimplemented
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ECCPASE
CMVREN
T1GINV
PRSEN
CMON
ADFM
IRP
Bit 7
P1M
GIE
—
—
—
—
—
(1)
TOUTPS3
ECCPAS2
TMR1GE
RP1
COUT
VCFG
PDC6
PEIE
ADIF
Bit 6
—
—
—
—
—
(1)
TOUTPS2
ECCPAS1
T1CKPS1
CCP1IF
DC1B1
CMOE
PDC5
Bit 5
GP5
T0IE
VRR
RP0
—
—
—
TOUTPS1
ECCPAS0
T1CKPS0
CMPOL
FVREN
DC1B0
T1ACS
PDC4
CHS2
INTE
Preliminary
Bit 4
GP4
TO
—
Write Buffer for upper 5 bits of Program Counter
T1OSCEN
TOUTPS0
CCP1M3
PSSAC1
CMHYS
PDC3
CHS1
GPIE
CMIF
Bit 3
GP3
VR3
PD
—
—
TMR2ON
CCP1M2
T1SYNC
PSSAC0
PDC2
CHS0
CMR
Bit 2
GP2
T0IF
VR2
—
—
Z
GO/DONE
T2CKPS1
TMR1CS
CCP1M1
PSSBD1
TMR2IF
T1GSS
PDC1
INTF
Bit 1
GP1
VR1
DC
—
—
© 2006 Microchip Technology Inc.
T2CKPS0 -000 0000
CMSYNC
TMR1ON
CCP1M0
PSSBD0
TMR1IF
CMCH
ADON
PDC0
GPIF
Bit 0
GP0
VR0
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
---0 0000
0000 0000
-00- 0-00
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
XXXX XXXX
XXXX XXXX
0-00 0000
0000 0000
0000 0000
0-00 0000
0000 -0-0
---0 0-10
xxxx xxxx
00-0 0000
POR, BOR
Value on
—
—
—
—
—
—
—
—
22, 101
41, 101
22, 101
15, 101
22, 101
31, 101
22, 101
17, 101
19, 101
45, 101
45, 101
49, 101
51, 101
52, 101
76, 101
76, 101
75, 101
91, 101
88, 101
62, 101
58, 101
59, 101
71, 101
70, 101
Page
—
—
—
—
—
—
—
—
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