PIC12F615-I/MD Microchip Technology, PIC12F615-I/MD Datasheet - Page 11
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PIC12F615-I/MD
Manufacturer Part Number
PIC12F615-I/MD
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(26 pages)
3.PIC12F609T-ISN.pdf
(8 pages)
4.PIC12F615-ESN.pdf
(168 pages)
Specifications of PIC12F615-I/MD
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
3
Digital Ic Case Style
DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F615-ESN PDF datasheet #4
- Current page: 11 of 212
- Download datasheet (2Mb)
2.0
2.1
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1:
2010 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
Wraps to 0000h-03FFh
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC<12:0>
Memory
13
PIC12F609/615/617/12HV609/615
0000h
0004h
0005h
03FFh
0400h
1FFFh
FIGURE 2-2:
2.2
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. The RP0 bit of the STATUS register is the
bank select bit.
RP0
0
1
Note:
Program
On-Chip
Memory
CALL, RETURN
RETFIE, RETLW
Data Memory Organization
Bank 0 is selected
Bank 1 is selected
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
Wraps to 0000h-07FFh
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
PC<12:0>
Page 0
13
DS41302D-page 11
1FFFh
0000h
0004h
0005h
07FFh
0800h
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