ATTINY25-20SSU Atmel, ATTINY25-20SSU Datasheet - Page 95

• Manufacturer Part Number: ATTINY25-20SSU
• Description: MCU AVR 2K ISP FLASH 2.7V 8-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SSU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 8SOIC W
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.4
12.3.5
12.3.6
12.3.7
2586M–AVR–07/10
OCR1A –Timer/Counter1 Output Compare RegisterA
OCR1B – Timer/Counter1 Output Compare RegisterB
OCR1C – Timer/Counter1 Output Compare RegisterC
TIMSK – Timer/Counter Interrupt Mask Register
The output compare register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and
OCR1A to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.
This register has the same function in normal mode and PWM mode.
Bit
0x2E
Read/Write
Initial value
Bit
0x2B
Read/Write
Initial value
Bit
0x2D
Read/Write
Initial value
Bit
0x39
Read/Write
Initial value
MSB
MSB
MSB
R/W
R/W
R/W
R
7
–
0
7
0
7
0
7
1
OCIE1A
R/W
R/W
R/W
R/W
6
0
6
0
6
1
6
0
OCIE1B
R/W
R/W
R/W
5
0
5
0
5
1
R/W
5
0
R/W
R/W
R/W
OCIE0A
4
0
4
0
4
1
R/W
4
0
R/W
R/W
R/W
3
0
3
0
3
1
OCIE0B
R/W
3
0
R/W
R/W
R/W
2
0
2
0
2
1
TOIE1
R/W
2
0
R/W
R/W
R/W
1
0
1
0
1
1
TOIE0
R/W
1
0
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
0
0
1
R
0
–
0
OCR1A
OCR1B
OCR1C
TIMSK
95