DSPIC33FJ32MC204-I/ML Microchip Technology, DSPIC33FJ32MC204-I/ML Datasheet

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... Microchip Technology Inc. dsPIC33FJ16MC304 Data Sheet High-Performance, 16-bit Digital Signal Controllers Preliminary DS70283G ...

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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to two channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode  2009 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Controller: • 5-cycle latency • available interrupt sources • ...

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... LIN bus support ® - IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin QFN/TQFP Note: See Table 1 for the exact peripheral features per device. Preliminary  2009 Microchip Technology Inc. ...

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... The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES Device Pins dsPIC33FJ32MC202 dsPIC33FJ32MC204 dsPIC33FJ16MC304 Note 1: Only two out of three timers are remappable. 2: Only PWM fault inputs are remappable ...

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... V INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6 PWM1L2/RP13 1 21 PWM1H2/RP12 2 20 PGEC2/EMUC2/TMS/PWM1L3/RP11 3 19 dsPIC33FJ32MC202 PGED2/EMUD2/TDI/PWM1H3/RP10 CAP TDO/PWM2L1/SDA1/RP9 externally. Preliminary = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN24/RB6 = Pins are tolerant (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 /V DDCORE (1) /CN21/RB9  2009 Microchip Technology Inc. ...

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... Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected  2009 Microchip Technology Inc PWM1L2/RP13 11 PWM1H2/RP12 10 PGEC2/EMUC2/PWM1L3/RP11 9 PGED2/EMUD2/PWM1H3/RP10 8 V CAP 7 dsPIC33FJ32MC204 dsPIC33FJ16MC304 RP25/CN19/RC9 5 RP24/CN20/RC8 4 PWM2L1/RP23 3 PWM2H1/RP22 2 SDA1/RP9 externally. Preliminary ...

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... SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. DS70283G-page 8 11 PWM1L2/RP13 10 PWM1H2/RP12 9 PGEC2/EMUC2/PWM1L3/RP11 8 PGED2/EMUD2/PWM1H3/RP10 CAP DDCORE dsPIC33FJ32MC204 dsPIC33FJ16MC304 (1) 5 RP25 /CN19/RC9 (1) 4 RP24 /CN20/RC8 3 PWM2L1/RP23 2 PWM2H1/RP22 1 SDA1/RP9 Preliminary = Pins are tolerant ...

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... High Temperature Electrical Characteristics ............................................................................................................................ 269 26.0 Packaging Information.............................................................................................................................................................. 279 Appendix A: Revision History............................................................................................................................................................. 289 Index ................................................................................................................................................................................................. 297 The Microchip Web Site ..................................................................................................................................................................... 301 Customer Change Notification Service .............................................................................................................................................. 301 Customer Support .............................................................................................................................................................................. 301 Reader Response .............................................................................................................................................................................. 302 Product Identification System ............................................................................................................................................................ 303  2009 Microchip Technology Inc. Preliminary DS70283G-page 9 ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70283G-page 10 Preliminary  2009 Microchip Technology Inc. ...

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... This document contains device-specific information for the following Digital Signal Controller (DSC) devices: • dsPIC33FJ32MC202 • dsPIC33FJ32MC204 • dsPIC33FJ16MC304 The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. ...

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... Control Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR OC/ SPI1 ADC1 PWM1-2 QEI CNx I2C1 Preliminary PORTA PORTB 16 PORTC Remappable Pins 16-bit ALU 16 PWM 2 Ch PWM 6 Ch  2009 Microchip Technology Inc. ...

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... No Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select  2009 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...

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... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input Output; Preliminary P = Power I = Input  2009 Microchip Technology Inc. ...

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... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source.  2009 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...

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... Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL  2009 Microchip Technology Inc. is ...

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... Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749  2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” ...

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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. DS70283G-page Preliminary  2009 Microchip Technology Inc. ...

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... Figure 3-2.  2009 Microchip Technology Inc. 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory. Each memory block has its own independent Address Generation Unit (AGU) ...

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... Data Latch PCL X RAM Y RAM Address Loop Address Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules  2009 Microchip Technology Inc. ...

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... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH  2009 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...

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... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70283G-page 22 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0  2009 Microchip Technology Inc. ...

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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).  2009 Microchip Technology Inc. (2) Preliminary DS70283G-page 23 ...

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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70283G-page 24 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set  2009 Microchip Technology Inc. ...

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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.  2009 Microchip Technology Inc. Preliminary DS70283G-page 25 ...

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... Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. TABLE 3-1: Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC Preliminary DSP INSTRUCTIONS SUMMARY Algebraic ACC Write Operation Back Yes Yes change in A Yes Yes  2009 Microchip Technology Inc. ...

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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In  2009 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70283G-page 27 ...

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... OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. Preliminary Adder/Subtracter, Overflow and Saturation previously and the SAT<A:B> trap when set and  2009 Microchip Technology Inc. the ...

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... MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction  2009 Microchip Technology Inc. into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: • ...

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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. Preliminary  2009 Microchip Technology Inc. ...

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... Device Configuration 0xF80000 Registers 0xF80017 0xF80018 Reserved 0xFEFFFE 0xFF0000 DEVID (2) 0xFFFFFE  2009 Microchip Technology Inc. 4.1 Program Address Space The program address dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 and devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program ...

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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006  2009 Microchip Technology Inc. ...

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... Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2009 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...

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... Optionally Mapped into Program Memory 0xFFFF DS70283G-page 34 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space  2009 Microchip Technology Inc. ...

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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class).  2009 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths ...

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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...

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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...

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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...

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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...

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TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...

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TABLE 4-10: QEI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name — QEI1CON 01E0 CNTERR QEISIDL INDEX DFLT1CON 01E2 — — — — POS1CNT 01E4 MAX1CNT 01E6 Legend uninitialized bit, — = unimplemented, ...

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TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...

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... TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC ...

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TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...

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... TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...

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... ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. TABLE 4-22: PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC — ...

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TABLE 4-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...

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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary  2009 Microchip Technology Inc. addressing modes are ...

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... Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes.  2009 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...

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... MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary Modulo Addressing EA the difference between the  2009 Microchip Technology Inc. ...

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... Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment  2009 Microchip Technology Inc. If the length of a bit-reversed buffer the last ‘N’ bits of the data buffer start address must be zeros. ...

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... TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70283G-page 52 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal  2009 Microchip Technology Inc. ...

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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>.  2009 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...

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... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70283G-page 54 Program Counter 0 23 bits TBLPAG 1/0 8 bits 24 bits Select 1 PSVPAG 0 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select  2009 Microchip Technology Inc. ...

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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG  2009 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...

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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address.  2009 Microchip Technology Inc. ...

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... Table Instruction User/Configuration Space Select  2009 Microchip Technology Inc. customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be pro- grammed ...

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... PROGRAMMING TIME T  %   % FRC Accuracy FRC Tuning 11064 Cycles =       0.05 1 0.00375 – 11064 Cycles =       1 0.05 – 1 0.00375 –  2009 Microchip Technology Inc. ...

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... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented.  2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...

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... NVMKEY<7:0>: Key Register (write-only) bits DS70283G-page 60 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP  2009 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...

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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary  2009 Microchip Technology Inc. ...

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... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch  2009 Microchip Technology Inc. • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset A simplified block diagram of the Reset module is shown in Figure 6-1. Any active source of reset will make the SYSRST signal active ...

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... SWDTEN bit setting. DS70283G-page 64 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown  2009 Microchip Technology Inc. ...

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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary ...

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... PWRT have stabilized at the has elapsed, the SYSRST for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 s for a OST  2009 Microchip Technology Inc. ...

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... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T  2009 Microchip Technology Inc. Vbor V BOR ...

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... DD ) for proper device operation. The BOR crosses DD has elapsed. The BOR ensures the voltage regulator output ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point BOR  2009 Microchip Technology Inc. DD ...

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... Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence.  2009 Microchip Technology Inc BOR PWRT ...

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... W register access or Security Reset Configuration Mismatch MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR — —  2009 Microchip Technology Inc. ...

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... These are summarized in Table 7-1 and Table 7-2.  2009 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...

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... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70283G-page 72 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1)  2009 Microchip Technology Inc. ...

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... Microchip Technology Inc. AIVT Address 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...

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... FLTA1 – PWM1 Fault A Reserved U1E – UART1 Error Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWM2 – PWM2 Period Match FLTA2 – PWM2 Fault A Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved  2009 Microchip Technology Inc. ...

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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.  2009 Microchip Technology Inc. 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...

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... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set  2009 Microchip Technology Inc. ...

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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...

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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70283G-page 78 Preliminary  2009 Microchip Technology Inc. ...

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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...

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... Interrupt request has not occurred DS70283G-page 80 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown  2009 Microchip Technology Inc. ...

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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009 Microchip Technology Inc. Preliminary DS70283G-page 81 ...

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... Interrupt request has not occurred DS70283G-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown  2009 Microchip Technology Inc. ...

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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEIIF U-0 ...

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... Unimplemented: Read as ‘0’ DS70283G-page 84 U-0 U-0 R/W-0 — — FLTA2IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R/W-0 U-0 PWM2IF — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown ...

Page 85

... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...

Page 86

... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283G-page 86 Preliminary  2009 Microchip Technology Inc. ...

Page 87

... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...

Page 88

... Unimplemented: Read as ‘0’ DS70283G-page 88 U-0 U-0 R/W-0 — — QEIIE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...

Page 89

... Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...

Page 90

... Interrupt is priority 1 000 = Interrupt source is disabled DS70283G-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 91

... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...

Page 92

... Interrupt is priority 1 000 = Interrupt source is disabled DS70283G-page 92 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 93

... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...

Page 94

... Interrupt is priority 1 000 = Interrupt source is disabled DS70283G-page 94 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 95

... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled  2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...

Page 96

... Unimplemented: Read as ‘0’ DS70283G-page 96 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 97

... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...

Page 98

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 99

... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — ...

Page 100

... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70283G-page 100 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 101

... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2009 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...

Page 102

... NOTES: DS70283G-page 102 Preliminary  2009 Microchip Technology Inc. ...

Page 103

... LPOSCEN SOSCI Note 1: See Figure 8-2 for PLL details the Oscillator is used with modes, an external parallel resistor with the value of 1 M must be connected.  2009 Microchip Technology Inc. The dsPIC33FJ16MC304 oscillator system provides: • External and internal oscillator options as clock sources. • ...

Page 104

... MIPS. Preliminary SYSTEM CLOCK SELECTION Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> is divided OSC ) and the defines the given by: CY DEVICE OPERATING FREQUENCY F OSC F = ------------- CY 2 PLL CONFIGURATION factor ‘N1’ is selected using  2009 Microchip Technology Inc. the ...

Page 105

... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device.  2009 Microchip Technology Inc. ’, • If PLLDIV<8:0> = 0x1E, then 32. This yields a VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...

Page 106

... PLL modes. DS70283G-page 106 (1) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary  2009 Microchip Technology Inc. R/W-y R/W-y (2) NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...

Page 107

... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2009 Microchip Technology Inc. (1) (CONTINUED) ...

Page 108

... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70283G-page 108 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 109

... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...

Page 110

... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70283G-page 110 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 111

... The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this  2009 Microchip Technology Inc. case, the OSWEN bit is cleared automatically and the clock switch is aborted. 2. ...

Page 112

... NOTES: DS70283G-page 112 Preliminary  2009 Microchip Technology Inc. ...

Page 113

... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2009 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have two special power-saving modes that are ...

Page 114

... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC  2009 Microchip Technology Inc. ...

Page 115

... AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T2MD ...

Page 116

... DS70283G-page 116 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 117

... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...

Page 118

... NOTES: DS70283G-page 118 Preliminary  2009 Microchip Technology Inc. ...

Page 119

... WR Port Data Latch Read LAT Read Port  2009 Microchip Technology Inc. the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected ...

Page 120

... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary dsPIC33FJ32MC202/204 and in response to a  2009 Microchip Technology Inc. ...

Page 121

... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped.  2009 Microchip Technology Inc. 10.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...

Page 122

... QEB RPINR14 INDX RPINR15 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1 RPINR20 SS1 RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEA1R<4:0> QEB1R<4:0> INDX1R<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0>  2009 Microchip Technology Inc. ...

Page 123

... RPnR<4:0> NULL U1TX U1RTS SDO1 SCK1OUT SS1OUT OC1 OC2 UPDN  2009 Microchip Technology Inc. FIGURE 10-3: U1TX Output Enable U1RTS Output Enable 4 OC2 Output Enable UPDN Output Enable U1TX Output U1RTS Output UPDN Output RPn tied to default port pin 00000 ...

Page 124

... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. Preliminary  2009 Microchip Technology Inc. ...

Page 125

... Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. and R/W-1 R/W-1 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 126

... Input tied to RP0 DS70283G-page 126 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> Bit is unknown  2009 Microchip Technology Inc. bit 8 bit 0 ...

Page 127

... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...

Page 128

... Input tied to RP1 00000 = Input tied to RP0 DS70283G-page 128 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 8 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 129

... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...

Page 130

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> Bit is unknown U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 FLTA1R<4:0> Bit is unknown  2009 Microchip Technology Inc. bit 8 bit 0 bit 8 bit 0 ...

Page 131

... FLTA2R<4:0>: Assign PWM2 Fault (FLTA2) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ...

Page 132

... Input tied to RP1 00000 = Input tied to RP0 DS70283G-page 132 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Bit is unknown  2009 Microchip Technology Inc. bit 8 bit 0 ...

Page 133

... INDX1R<4:0>: Assign QEI INDEX (INDX) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ...

Page 134

... Input tied to RP1 00000 = Input tied to RP0 DS70283G-page 134 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> Bit is unknown  2009 Microchip Technology Inc. bit 8 bit 0 ...

Page 135

... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...

Page 136

... Input tied to RP0 DS70283G-page 136 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 SS1R<4:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 137

... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers)  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...

Page 138

... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 139

... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for peripheral function numbers)  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...

Page 140

... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 141

... RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 10-2 for peripheral function numbers)  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R< ...

Page 142

... Bit is cleared R/W-0 R/W-0 R/W-0 RP23R<4:0> R/W-0 R/W-0 R/W-0 RP22R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 143

... RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-2 for peripheral function numbers)  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R< ...

Page 144

... NOTES: DS70283G-page 144 Preliminary  2009 Microchip Technology Inc. ...

Page 145

... SOSCI TGATE 1 Set T1IF 0 Reset Equal  2009 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal ...

Page 146

... DS70283G-page 146 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 147

... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an generated with the Timer3 interrupt flags.  2009 Microchip Technology Inc. 12.1 32-bit Operation To configure the Timer2/3 feature timers for 32-bit operation: 1. Set the T32 control bit. ...

Page 148

... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70283G-page 148 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync  2009 Microchip Technology Inc. ...

Page 149

... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal  2009 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70283G-page 149 ...

Page 150

... DS70283G-page 150 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 151

... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect.  2009 Microchip Technology Inc. U-0 U-0 (1) — ...

Page 152

... NOTES: DS70283G-page 152 Preliminary  2009 Microchip Technology Inc. ...

Page 153

... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel.  2009 Microchip Technology Inc. 1. Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin 2 ...

Page 154

... DS70283G-page 154 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE HC = Cleared in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 155

... TMR3 TMR2  2009 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value ...

Page 156

... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary —  2009 Microchip Technology Inc. ...

Page 157

... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled  2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 158

... NOTES: DS70283G-page 158 Preliminary  2009 Microchip Technology Inc. ...

Page 159

... Fault pins to optionally drive each of the PWM output pins to a defined state. Duty cycle updates configurable to be immediate or synchronized to the PWM time base.  2009 Microchip Technology Inc. 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...

Page 160

... Generator 2 PWM Channel 1 Dead-Time Generator 1 Special Event Postscaler SEVTDIR PTDIR Preliminary PWM1H3 Generator and PWM1L3 Override Logic PWM1H2 Generator and Output PWM1L2 Override Logic Driver PWM1H1 Block Generator and PWM1L1 Override Logic FLTA1 Special Event Trigger  2009 Microchip Technology Inc. ...

Page 161

... P2FLTACON P2OVDCON P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base  2009 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFRs Fault Pin Control SFRs PWM Manual Control SFR PWM Generator 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time ...

Page 162

... R/W-0 R/W-0 R/W-0 PTCKPS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1:64 prescale) CY (1:16 prescale) CY (1:4 prescale) CY (1:1 prescale) CY Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 PTMOD<1:0> bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 163

... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...

Page 164

... SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) TMR<15>) to generate the Special Event Trigger. X TMR<14:0> to generate the Special Event Trigger. X Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 165

... PWMxL pin disabled, I/O pin becomes general purpose I/O Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair.  2009 Microchip Technology Inc. (2) U-0 U-0 — ...

Page 166

... Updates from Duty Cycle and Period Buffer registers are enabled DS70283G-page 166 U-0 R/W-0 R/W-0 — SEVOPS<3:0> U-0 U-0 R/W-0 — — IUE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared boundary CY Preliminary  2009 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 OSYNC UDIS bit Bit is unknown ...

Page 167

... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 ...

Page 168

... DS70283G-page 168 (1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DTS3I DTS2A DTS2I U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 DTS1A DTS1I bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 169

... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair.  2009 Microchip Technology Inc. (1) R/W-0 R/W-0 R/W-0 FAOV3L ...

Page 170

... DS70283G-page 170 (1) R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 171

... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC2<15:0>: PWM Duty Cycle 2 Value bits  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 172

... PDC3<15:0>: PWM Duty Cycle 3 Value bits DS70283G-page 172 R/W-0 R/W-0 R/W-0 PDC3<15:8> R/W-0 R/W-0 R/W-0 PDC3<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 173

... Existing Pin Logic 0 UPDNx Up/Down 1  2009 Microchip Technology Inc. This section describes the Quadrature Encoder Inter- face (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. The operational features of the QEI include: • ...

Page 174

... The POSCNT register accesses. However, reading the register in Byte mode can result in partially updated values in subsequent reads. Either use Word mode reads/writes, or ensure that the counter is not counting during Byte operations. DS70283G-page 174 allows byte Preliminary  2009 Microchip Technology Inc. ...

Page 175

... Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled  2009 Microchip Technology Inc. R-0 R/W-0 R/W-0 INDEX UPDN ...

Page 176

... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. DS70283G-page 176 Preliminary  2009 Microchip Technology Inc. ...

Page 177

... Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’  2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — IMV<1:0> U-0 U-0 — ...

Page 178

... NOTES: DS70283G-page 178 Preliminary  2009 Microchip Technology Inc. ...

Page 179

... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF  2009 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, analog-to-digital converters, etc. ...

Page 180

... DS70283G-page 180 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary  2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...

Page 181

... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1.  2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...

Page 182

... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70283G-page 182 (3) (3) Preliminary  2009 Microchip Technology Inc. ...

Page 183

... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application  2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 184

... NOTES: DS70283G-page 184 Preliminary  2009 Microchip Technology Inc. ...

Page 185

... I C supports multi-master operation, detects bus collision and arbitrates accordingly.  2009 Microchip Technology Inc. 18.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing. ...

Page 186

... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read  2009 Microchip Technology Inc. ...

Page 187

... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching  2009 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...

Page 188

... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70283G-page 188 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master) Preliminary 2 C master)  2009 Microchip Technology Inc. ...

Page 189

... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.  2009 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...

Page 190

... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70283G-page 190 2 C slave device address byte. Preliminary  2009 Microchip Technology Inc. ...

Page 191

... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position  2009 Microchip Technology Inc. U-0 U-0 U-0 — ...

Page 192

... NOTES: DS70283G-page 192 Preliminary  2009 Microchip Technology Inc. ...

Page 193

... Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter  2009 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins • Even, Odd or No Parity Options (for 8-bit data) • ...

Page 194

... DS70283G-page 194 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown  2009 Microchip Technology Inc. ...

Page 195

... Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor- mation on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0).  2009 Microchip Technology Inc. MODE REGISTER (CONTINUED) x ...

Page 196

... R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Clear only bit x = Bit is unknown  2009 Microchip Technology Inc. ...

Page 197

... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor- mation on enabling the UART module for transmit operation.  2009 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...

Page 198

... NOTES: DS70283G-page 198 Preliminary  2009 Microchip Technology Inc. ...

Page 199

... Four result alignment options (signed/unsigned, fractional/integer) • Operation during CPU Sleep and Idle modes • 16-word conversion result buffer  2009 Microchip Technology Inc. The 12-bit ADC configuration supports all the above features, except: • In the 12-bit configuration, conversion speeds 500 ksps are supported. • ...

Page 200

... FIGURE 20-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND dsPIC33FJ32MC204 DEVICES AN0 AN8 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 V - REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN7 ...