PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet - Page 3
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PIC18F2220-I/SP
Manufacturer Part Number
PIC18F2220-I/SP
Description
IC MCU FLASH 2KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2220-ISO.pdf
(394 pages)
3.PIC18F2220-ISO.pdf
(6 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(8 pages)
6.PIC18F2220-ISO.pdf
(6 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISP.pdf
(388 pages)
Specifications of PIC18F2220-I/SP
Program Memory Type
FLASH
Program Memory Size
4KB (2K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
5
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2220-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4. Module: Oscillator
© 2009 Microchip Technology Inc.
The 32 kHz internal oscillator, INTRC, will be held
in Reset if either of the following is enabled:
• Power-up Timer
• High-Speed Crystal/Resonator with PLL
Without the INTRC oscillator running, the Power-up
Timer and Phase Locked Loop (PLL) timer will not
expire
device will not exit Reset. This issue does not affect
the Watchdog Timer or any other mode.
The provided work arounds require only two
modifications to the Configuration Word values.
No additional changes to the application hardware
or software are necessary, except as noted below.
Work around: Power-up Timer
Disable the Power-up Timer by programming
PWRTEN (CONFIG2L<0>) to ‘1’. This results in a
shorter time before the microcontroller begins to
execute code after power up or exiting from Sleep
mode or from Brown-out Reset (if enabled).
If a power-up delay is needed to ensure a stable
V
feature. The BOR keeps the device in Reset until
the specified V
This work around is available by programming the
BOR bit to ‘1’ and selecting BOR voltage bits with
BORV<1:0> bits in the CONFIG2L Configuration
Word.
If BOR is not enabled and additional start-up delay
is needed, consider implementing an external
system supervisor to keep the microcontroller in
Reset until the V
consider use of an equivalent PIC18F4321 device.
Work around: HSPLL Oscillator Mode
Two work arounds are available through the
Configuration bits. Enabling either of the following
features permits the HSPLL mode to work
successfully:
• Two-Speed Start-up
• Fail-Safe Clock Monitor
DD
Enabled (HSPLL) Oscillator mode
, consider using the Brown-out Reset (BOR)
and
DD
the
has been achieved.
DD
PIC18F2220/2320/4220/4320
has stabilized. Alternately,
PIC18F2220/2320/4220/4320
Both options permit the microcontroller to start
from the 32 kHz INTRC after power-up, BOR, or
wake-up from Sleep mode. The options also
permit code to execute while PLL is waiting to lock.
The PLL lock time typically is 2 ms which results in
approximately 16 instruction executions before the
switch to the HSPLL clock occurs. If typical initial-
ization code is performed after a Power-on Reset
or Brown-out Reset, the impact of this work around
should be negligible.
If Sleep mode is used, both work arounds result in
code execution during PLL lock time. A software
delay may be needed to avoid executing time-crit-
ical
(OSCCON<3>) bit will set to indicate when the
HSPLL is ready and time-critical code can be
executed.
The Two-Speed Start-up and Fail-Safe Clock
Monitor work arounds switch the system clock
source from INTRC to HSPLL mode after a PLL
lock occurs. This is handled automatically by the
microcontroller and requires no additional soft-
ware or special monitoring. For more information,
see Section 2.7 “Clock Sources and Oscillator
Switching” in the “PIC18F2220/2320/4220/4320
Data Sheet” (DS39599).
Date Codes that pertain to this issue:
Engineering and production devices with a date
code of 0813 or later may be affected.
code
after
wake-up.
DS80396B-page 3
The
OSTS