PIC18LF2455-I/SP Microchip Technology, PIC18LF2455-I/SP Datasheet - Page 15
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PIC18LF2455-I/SP
Manufacturer Part Number
PIC18LF2455-I/SP
Description
IC PIC MCU FLASH 12KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18LF4550-IML.pdf
(430 pages)
Specifications of PIC18LF2455-I/SP
Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
2048Byte
Cpu Speed
48MHz
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
33. Module: Timer1/3
EXAMPLE 6:
34. Module: Resets (BOR)
© 2009 Microchip Technology Inc.
CLRF
MOVLW
MOVWF
For Timer1 or Timer3, if the TMRxH and TMRxL
registers are written to in consecutive instruction
cycles, the timer may not be updated with the
correct value if it is configured for externally
clocked, 8-Bit Asynchronous mode (T1CON<7:0>
or T3CON<7:0> = 0xxx x111).
For the purposes of this issue, instructions that
directly affect the contents of the Timer registers
are considered to be writes. This includes CLRF,
SETF and MOVF instructions.
Work around
Insert a delay of one or more instruction cycles
between writes to TMRxH and TMRxL. This delay
can be a NOP, or any instruction that does not
access the Timer registers (Example 6).
Affected Silicon Revisions
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with high device operating frequencies, some table
read operations and heavy loading on the USB
voltage regulator. When all of these conditions are
present, BOR has been observed with V
20 percent higher than the V
for a given BORV<1:0> setting.
The BOR threshold may decrease under other
conditions, such as during Sleep, where it may not
occur until V
minimums.
Work around
None.
Affected Silicon Revisions
A3
A3
TMR1H
T1Offset
TMR1L
B4
B4
DD
X
X
TIMER1/3 – CONSECUTIVE
WRITES
is 120 mV below the specified
; 1 Tcy delay
B5
B5
X
BOR
B6
B6
X
value specified
PIC18F2455/2550/4455/4550
B7
B7
DD
35. Module: Resets (BOR)
36. Module: EUSART
37. Module: MSSP (SPI Slave)
Certain operating conditions can move the effec-
tive Brown-out Reset (BOR) threshold outside of
the range specified in the electrical characteristics
of the Device Data Sheet (parameter D005).
The BOR threshold has been observed to increase
with some table read operations. BOR has been
observed with 7 percent higher V
value specified for a given BORV<1:0> setting.
Work around
None.
Affected Silicon Revisions
In Synchronous Master mode, while transmitting
the Most Significant data bit, the data line (DT)
may change state before the bit finishes transmit-
ting. If the receiver samples the data line later than
0.5 bit times + 1.5 T
starting edge of the MSb, the bit may be read
incorrectly.
Work around
None.
Affected Silicon Revisions
If configured in SPI Slave mode, the MSSP may not
successfully recognize data packets generated by an
external master processor. This applies to all SPI
Slave modes (CKE/CKP = 1 or 0), whether or not
slave select is enabled (SSPM<3:0> = 010x).
Work around
Insert a series resistor between the SPI master
Serial Data Out (SDO) and the corresponding SPI
slave Serial Data In (SDI) input line of the
microcontroller. The required value for the resistor
varies with the application system’s characteristics
and
microcontrollers.
Experimentation
encouraged.
Affected Silicon Revisions
A3
A3
A3
the
process
B4
B4
B4
X
X
and
CY
variations
B5
B5
B5
X
X
(of the master) after the
thorough
DS80478A-page 15
DD
B6
B6
B6
X
between
than the V
testing
B7
B7
B7
X
BOR
the
are