PIC16LF874-04/P Microchip Technology, PIC16LF874-04/P Datasheet - Page 21
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PIC16LF874-04/P
Manufacturer Part Number
PIC16LF874-04/P
Description
IC MCU FLASH 4KX14 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
128Byte
Ram Memory Size
192Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF874-04/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC16LF874-04/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16LF874-04/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC16LF874-04/PT
Manufacturer:
MICROCHIP
Quantity:
19 800
Company:
Part Number:
PIC16LF874-04/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
2.2.2.2
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
2001 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note:
OPTION_REG Register
When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3
in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper-
ation of the device
OPTION_REG REGISTER (ADDRESS 81h, 181h)
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
bit 7
Legend:
R = Readable bit
- n = Value at POR
R/W-1
RBPU
000
001
010
011
100
101
110
111
INTEDG
R/W-1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
R/W-1
T0CS
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
W = Writable bit
’1’ = Bit is set
R/W-1
T0SE
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-1
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
PSA
R/W-1
PS2
PIC16F87X
x = Bit is unknown
R/W-1
PS1
DS30292C-page 19
R/W-1
PS0
bit 0