PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 120
![IC MCU CAN FLASH 8K LP 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 120 of 402
- Download datasheet (7Mb)
13.2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
TABLE 13-1:
DS41159E-page 118
PIC18FXX8
INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
Legend:
Note 1:
Name
Timer2 Interrupt
Timer2 Module Register
Timer2 Period Register
PSPIF
PSPIE
PSPIP
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 7
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
F
—
OSC
(1)
(1)
(1)
/4
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TIMER2 BLOCK DIAGRAM
ADIF
ADIE
ADIP
Bit 6
T2CKPS1:T2CKPS0
1:1, 1:4, 1:16
TMR0IE
Prescaler
RCIF
RCIE
RCIP
Bit 5
2
INT0IE
TXIE
TXIP
Bit 4
TXIF
Comparator
TMR2
PR2
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
13.3
The output of TMR2 (before the postscaler) is a clock
input to the Synchronous Serial Port module which
optionally uses it to generate the shift clock.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
EQ
Reset
Bit 2
TOUTPS3:TOUTPS0
Postscaler
1:1 to 1:16
Output of TMR2
TMR2IF
TMR2IE
TMR2IP
INT0IF
Bit 1
TMR2
Output
4
(1)
TMR1IE
TMR1IP
TMR1IF
Bit 0
RBIF
© 2006 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
POR, BOR
bit TMR2IF
Value on
Sets Flag
Value on
all other
Resets
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