LPC1112FHN33/201,5 NXP Semiconductors, LPC1112FHN33/201,5 Datasheet - Page 20

• Manufacturer Part Number: LPC1112FHN33/201,5
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100r

Specifications of LPC1112FHN33/201,5

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC11
• Core: ARM Cortex M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 28
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M0
• Family Name: LPC1100
• Maximum Speed: 50 MHz
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4954; 935290774551

NXP Semiconductors
7. Functional description
LPC1111_12_13_14
Product data sheet
7.1 ARM Cortex-M0 processor
7.2 On-chip flash program memory
7.3 On-chip SRAM
7.4 Memory map
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
The LPC1111/12/13/14 contain 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or
8 kB (LPC1111) of on-chip flash memory.
The LPC1111/12/13/14 contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM memory.
The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the
following figures.
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
All information provided in this document is subject to legal disclaimers.
Figure 5
Rev. 4 — 10 February 2011
shows the overall map of the entire address space from the
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
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