Z8F0213HH005EG Zilog, Z8F0213HH005EG Datasheet - Page 111

• Manufacturer Part Number: Z8F0213HH005EG
• Description: IC ENCORE MCU FLASH 2K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4044; Z8F0213HH005EG

PS024314-0308
DE
1
0
1
0
Idle State
of Line
External Driver Enable
UART Interrupts
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in
when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the final Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data
Register before the previous character is completely transmitted) the DE signal is not
deasserted between characters. The
polarity of the Driver Enable signal.
The Driver Enable to Start bit setup time is calculated as follows:
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
Start


---------------------------------------- -
Baud Rate (Hz)
Bit0
lsb
1
Bit1


≤
Bit2
DE to Start Bit Setup Time (s)
Bit3
Data Field
DEPOL
Bit4
bit in the UART Control Register 1 sets the
Bit5
Figure
Universal Asynchronous Receiver/Transmitter
Bit6
14. The Driver Enable signal asserts
Z8 Encore! XP
≤


---------------------------------------- -
Baud Rate (Hz)
msb
Bit7
Product Specification
2
Parity
®
Stop Bit


F0823 Series
1
101